DAC3154
DAC3164
SLAS960 – MAY 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
BLOCK DIAGRAMS
DACCLKP
LVPECL
DACCLKN
DATACLKP LVDS
DATACLKN
DATA9P LVDS
DATA9N
Clock Distribution
Programmable
Delay
10
QMC
A-offset
1.2 V
Reference
EXTIO
BIASJ
DACA
Gain
10-b
DACA
IOUTAP
IOUTAN
DATA0P LVDS
DATA0N
SYNCP LVDS
SYNCN
ALIGNP
LVPECL
ALIGNN
10
Optional Input
Used for multi-DAC sync
QMC
B-offset
10-b
DACB
DACB
Gain
IOUTBP
IOUTBN
Control Interface
VDDA33
Figure 1. DAC3154
2
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