CYRF69303-40LFXC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
CYRF69303-40LFXC Datasheet PDF : 70 Pages
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CYRF69303
Pin Definitions (continued)
Pin
Name
Description
27
IRQ
Radio Function Interrupt output, configure High, Low or as Radio GPIO
28
P1.5 / MOSI MOSI pin from microcontroller function to radio function
29
MISO 3-wire SPI mode configured as Radio GPIO. In 4-wire SPI mode sends data to MCU function
30
XOUT Buffered CLK or Radio GPIO
31
NC
Must be floating
32
P1.6 GPIO
33
VIO
2.7 V to 3.6 V to main power supply rail for Radio I/O
34
RST
Radio Reset. Connected to VCC with 0.47 F. Must have a RST=HIGH event the very first time power
is applied to the radio otherwise the state of the radio control registers is unknown
35
P1.7 GPIO
36
VDD1.8 Regulated logic bypass. Connected to 0.47 F to GND
37
GND Must be connected to ground
38
P0.7 GPIO
39
Vbat0
Connected to 2.7 V to 3.6 V main power supply, through 0.047 F bypass C
41
E-pad Must be connected to ground
42
Corner Tabs Do Not connect corner tabs
Functional Block Overview
All the blocks that make up the PRoC LPstar are presented in
this section.
2.4 GHz Radio
The radio transceiver is a dual conversion low IF architecture
optimized for power and range/robustness. The radio employs
channel matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides up to 0 dBm transmit power, with an output power
control range of 30 dB in six steps. The supply current of the
device is reduced as the RF output power is reduced.
Table 1. Internal PA Output Power Step Table
PA Setting
6
5
4
Typical Output Power (dBm)
0
–5
–10
3
–15
2
–20
1
–25
0
–30
Frequency Synthesizer
Before transmission or reception may commence, it is necessary
for the frequency synthesizer to settle. The settling time varies
depending on channel; 25 fast channels are provided with a
maximum settling time of 100 s.
The “fast channels” (<100 s settling time) are every third
frequency, starting at 2400 MHz up to and including 2472 MHz
(that is, 0,3,6,9…….69 and 72).
Baseband and Framer
The baseband and framer blocks provide the DSSS encoding
and decoding, SOP generation and reception and CRC16
generation and checking, and EOP detection and length field.
Data Transmission Modes and Data Rates
The SoC supports two different data transmission modes:
■ In GFSK mode, data is transmitted at 1 Mbps, without any
DSSS.
■ In DSSS mode eight bits (8DR, 32 chip) are encoded in each
derived code symbol transmitted, resulting in effective 250 kbps
data rate.
32 chip Pseudo Noise (PN) codes are supported. The two data
transmission modes apply to the data after the SOP. In particular
the length, data, and CRC16 are all sent in the same mode. In
general, DSSS reduce packet error rate in any environment.
Link Layer Modes
SOP
Packets begin with a two-symbol SoP marker. If framing is
disabled then an SOP event is inferred whenever two successive
correlations are detected. The SOP_CODE_ADR code used for
the SOP is different from that used for the “body” of the packet,
and if desired may be a different length. SOP must be configured
to be the same length on both sides of the link.
Length
Length field is the first eight bits after the SOP symbol, and is
transmitted at the payload data rate. An EoP condition is inferred
after reception of the number of bytes defined in the length field,
plus two bytes for the CRC16.
Document Number: 001-66502 Rev. *D
Page 6 of 70
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