CY8C3865PVI-053(2011_03) View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

MFG CO.

CY8C3865PVI-053
(Rev.:2011_03)

Programmable System-on-Chip (PSoC®)

Cypress Semiconductor 

PSoC® 3: CY8C38 Family

Data Sheet

Table 4-2. Logical Instructions (continued)

Mnemonic

ANL Direct, #data

ORL A,Rn

Description

AND immediate data to direct byte

OR register to accumulator

ORL

ORL

ORL

A,Direct

A,@Ri

A,#data

OR direct byte to accumulator

OR indirect RAM to accumulator

OR immediate data to accumulator

ORL Direct, A

ORL Direct, #data

XRL A,Rn

OR accumulator to direct byte

OR immediate data to direct byte

XOR register to accumulator

XRL A,Direct

XRL A,@Ri

XRL A,#data

XOR direct byte to accumulator

XOR indirect RAM to accumulator

XOR immediate data to accumulator

XRL Direct, A

XRL Direct, #data

CLR A

XOR accumulator to direct byte

XOR immediate data to direct byte

Clear accumulator

CPL A

RL A

RLC A

Complement accumulator

Rotate accumulator left

Rotate accumulator left through carry

RR A

RRC A

SWAP A

Rotate accumulator right

Rotate accumulator right though carry

Swap nibbles within accumulator

Bytes

3

1

2

1

2

2

3

1

2

1

2

2

3

1

1

1

1

1

1

1

Cycles

3

1

2

2

2

3

3

1

2

2

2

3

3

1

1

1

1

1

1

1

4.3.1.3 Data Transfer Instructions

The data transfer instructions are of three types: the core RAM,

xdata RAM, and the lookup tables. The core RAM transfer

includes transfer between any two core RAM locations or SFRs.

These instructions can use direct, indirect, register, and

immediate addressing. The xdata RAM transfer includes only the

transfer between the accumulator and the xdata RAM location.

It can use only indirect addressing. The lookup tables involve

nothing but the read of program memory using the Indexed

addressing mode. Table 4-3 lists the various data transfer

instructions available.

4.3.1.4 Boolean Instructions

The 8051 core has a separate bit-addressable memory location.

It has 128 bits of bit addressable RAM and a set of SFRs that are

bit addressable. The instruction set includes the whole menu of

bit operations such as move, set, clear, toggle, OR, and AND

instructions and the conditional jump instructions. Table 4-4 lists

the available Boolean instructions.

Table 4-3. Data Transfer Instructions

Mnemonic

Description

Bytes

Cycles

MOV A,Rn

MOV A,Direct

MOV A,@Ri

Move register to accumulator

Move direct byte to accumulator

Move indirect RAM to accumulator

1

1

2

2

1

2

MOV A,#data

MOV Rn,A

MOV Rn,Direct

Move immediate data to accumulator

Move accumulator to register

Move direct byte to register

2

2

1

1

2

3

MOV

MOV

MOV

Rn, #data

Direct, A

Direct, Rn

Move immediate data to register

Move accumulator to direct byte

Move register to direct byte

2

2

2

2

2

2

Document Number: 001-11729 Rev. *R

Page 13 of 129

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