CY7C9689 View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

MFG CO.

CY7C9689

TAXI™ Compatible HOTLink® Transceiver

Cypress Semiconductor 

CY7C9689

Pin Descriptions (continued)

Pin

Name

31, 33 RXDATA[9:8]/

RXCMD[2:3]

23, 29 RXCMD[1:0]

69 RXEN

65 RXSC/D

I/O Characteristics

Signal Description

Three-state TTL out- Parallel Receive DATA or COMMAND Output.

put, changes following

RXCLK¦

When BYTE8/10 is HIGH and the decoder is enabled (ENCBYP is HIGH) these

outputs reflects the value for the most recently received RXCMD[2:3].

When BYTE8/10 is LOW and the decoder is enabled (ENCBYP is HIGH) these

outputs reflects the value for the most recently received RXDATA[9:8].

When the decoder is bypassed (ENCBYP is LOW), RXDATA[9:8] functions as

the 9th and 10th bits of the 10- or 12-bit non-decoded receive character.

When the Receive FIFO is disabled (FIFOBYP is LOW), these outputs change

on the rising edge of the RXCLK output. When the Receive FIFO is enabled

(FIFOBYP is HIGH), these outputs change on the rising edge of the RXCLK

input.

RXEN is a three-state control for RXDATA[9:8]/RXCMD[2:3].

Three-state TTL out- Parallel Receive COMMAND Outputs.

put, changes following When the decoder is enabled (ENCBYP is HIGH) these outputs reflect the value

RXCLK¦

for the most recently received RXCMD[1:0].

When BYTE8/10 is HIGH and the decoder is bypassed (ENCBYP is LOW),

these outputs have no meaning and are driven LOW.

When BYTE8/10 is LOW and the decoder is bypassed (ENCBYP is LOW),

RXCMD[1:0] functions as the 11th and 12th (MSB) bits of the 12-bit non-

decoded receive character.

When the Receive FIFO is disabled (FIFOBYP is LOW), this output changes on

the rising edge of the RXCLK output. When the Receive FIFO is enabled

(FIFOBYP is HIGH), these outputs change on the rising edge of the RXCLK

input.

RXEN is a three-state control for RXCMD[1:0].

TTL input, sampled

on RXCLK¦

Internal Pull-Up

Receive Enable Input.

RXEN is a three-state control for the parallel data bus read operations. RXEN

is sampled on the rising edge of the RXCLK input (or output) and enables

parallel data bus read operations (when selected). The device is selected when

RXEN is asserted during an RXCLK cycle immediately following one in which

CE is sampled LOW. The parallel data pins are driven to active levels after the

rising edge of RXCLK. When RXEN is de-asserted (ending the selection) the

parallel data pins are High-Z after the rising edge of RXCLK.

Depending on the level on EXTFIFO, this signal can be active HIGH or active

LOW. If EXTFIFO is LOW, then RXEN is active LOW. If EXTFIFO is HIGH, then

RXEN is active HIGH. Data is delivered on the clock cycle following any clock

edge when RXEN is active.

Three-state TTL out- COMMAND or DATA Output Indicator.

put, changes following When BYTE8/10 is HIGH and the decoder is enabled (ENCBYP is HIGH), this

RXCLK¦

output indicates which group of outputs have been updated. If RXSC/D is HIGH,

RXCMD[3:0] contains a new COMMAND. The DATA on the RXDATA[7:0] pins

remain unchanged. If RXSC/D is LOW, RXDATA[7:0] contains a new DATA char-

acter. The COMMAND output on RXCMD[3:0] remain unchanged.

When BYTE8/10 is LOW and the decoder is enabled (ENCBYP is HIGH), this

output indicates which group of outputs have been updated. If RXSC/D is HIGH,

RXCMD[1:0] contains a new COMMAND and the DATA on the RXDATA[9:0]

remain unchanged. If RXSC/D is LOW, RXDATA[9:0] contains a new DATA char-

acter and the COMMAND output on RXCMD[1:0] remain unchanged.

When the decoder is bypassed (ENCBYP is LOW) RXSC/D is not used and

may be left unconnected.

RXEN is a three-state control for RXSC/D.

7

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