CY7C441-14JC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
CY7C441-14JC Datasheet PDF : 15 Pages
| |||
CY7C441
CY7C443
Switching Characteristics Over the Operating Range[9]
7C441–12 7C441–14 7C441–20 7C441–30
7C443–12 7C443–14 7C443–20 7C443–30
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tCKW
Write Clock Cycle
12
14
20
30
ns
tCKR
Read Clock Cycle
12
14
20
30
ns
tCKH
Clock HIGH
5
6.5
9
12
ns
tCKL
tA[10]
Clock LOW
Data Access Time
5
6.5
9
12
ns
9
10
15
20 ns
tOH
Previous Output Data Hold After Read HIGH 0
0
0
0
ns
tFH
Previous Flag Hold After Read/Write HIGH 0
0
0
0
ns
tSD
Data Set-Up
4
5
6
7
ns
tHD
Data Hold
0
0
0
0
ns
tSEN
Enable Set-Up
4
5
6
7
ns
tHEN
Enable Hold
0
0
0
0
ns
tFD
tSKEW1[11]
tSKEW2[12]
Flag Delay
Opposite Clock After Clock
Opposite Clock Before Clock
9
10
15
20 ns
0
0
0
0
ns
12
14
20
30
ns
tPMR
Master Reset Pulse Width (MR LOW)
12
14
20
30
ns
tSCMR
Last Valid Clock LOW Set-Up to MR LOW
0
0
0
0
ns
tOHMR
Data Hold From MR LOW
0
0
0
0
ns
tMRR
Master Reset Recovery (MR HIGH Set-Up to 12
14
20
30
ns
First Enabled Write/Read)
tMRF
MR HIGH to Flags Valid
12
14
20
30 ns
tAMR
MR HIGH to Data Outputs LOW
12
14
20
30 ns
Notes:
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and output loading as shown in the AC Test Loads and Waveforms
and capacitance as in Note 7, unless otherwise specified.
10. Access time includes all data outputs switching simultaneously.
11. tSKEW1 is the minimum time an opposite clock can occur after a clock and still be guaranteed not to be included in the current clock cycle (for purposes of
flag update). If the opposite clock occurs less than tSKEW1 after the clock, the decision of whether or not to include the opposite clock in the current clock
cycle is arbitrary. Note: The opposite clock is the signal to which a flag is not synchronized; i.e., CKW is the opposite clock for Empty and Almost Empty flags,
CKR is the opposite clock for the Almost Full flag. The clock is the signal to which a flag is synchronized; i.e., CKW is the clock for the Almost Full flag, CKR
is the clock for Empty and Almost Empty flags.
12. tSKEW2 is the minimum time an opposite clock can occur before a clock and still be guaranteed to be included in the current clock cycle (for purposes of flag
update). If the opposite clock occurs less than tSKEW2 before the clock, the decision of whether or not to include the opposite clock in the current clock cycle
is arbitrary. See Note 11 for definition of clock and opposite clock.
Document #: 38-06032 Rev. *A
Page 4 of 15
Share Link: 