CY7C277-50TMB View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

MFG CO.

CY7C277-50TMB

32K x 8 Reprogrammable Registered PROM

Cypress Semiconductor 

CY7C277

Architecture Configuration Bits

Architecture Bit

ALE

Architecture Verify D7 - D0

D1

0 = DEFAULT

1 = PGMED

ALEP

D2

0 = DEFAULT

1 = PGMED

E/ES

D0

0 = DEFAULT

1 = PGMED

Bit Map

Programmer Address

(Hex.)

0000

.

.

.

7FFF

8000

RAM Data

Data

.

.

.

Data

Control Byte

Timing Diagram (Input Latched)[9]

A0 - A14

tAL

tLA

ALE

tLL

Function

Input Transparent

Input Latched

ALE = Active HIGH

ALE = Active LOW

Asynchronous Output Enable (E)

Synchronous Output Enable (ES)

Architecture Byte (8000)

D7

D0

C7 C6 C5 C4 C3 C2 C1 C0

tSA

tHA

ES

(SYNCH)

CP

O0 - O7

tHES

tCO

tSES

tHZC

tPWC

tHES

tPWC

HIGH Z

ES

(ASYNCH)

Timing Diagram (Input Transparent)

A0 - A14

ES

(SYNCH)

CP

O0 - O7

tHES

tCO

tSES

tHZC

tPWC

tHES

tPWC

HIGH Z

ES

(ASYNCH)

Note:

9. ALE is shown with positive polarity.

Document #: 38-04006 Rev. **

tSES

tLZC

tHZE

HIGHZ

tLZE

tSA

tHA

tSES

tLZC

tHZE

HIGHZ

tLZE

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