CY7C1348G View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

MFG CO.

CY7C1348G

4-Mbit (128K x 36) Pipelined DCD Sync SRAM

Cypress Semiconductor 

Switching Waveforms (continued)

Read/Write Timing[17, 19, 20]

tCYC

CLK

ADSP

tCH tCL

tADS tADH

ADSC

ADDRESS A1

tAS tAH

A2

BWE, BW[A:D]

tCES tCEH

CE

A3

A4

tWES tWEH

CY7C1348G

A5

A6

ADV

OE

Data In (D)

Data Out (Q)

tCO

tDS tDH

tOELZ

High-Z

D(A3)

tCLZ

tOEHZ

High-Z

Q(A1) Q(A2)

Back-to-Back READs

Single WRITE

Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)

BURST READ

DON’T CARE

UNDEFINED

Notes:

19. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

20. GW is HIGH.

D(A5) D(A6)

Back-to-Back

WRITEs

Document #: 38-05608 Rev. *D

Page 13 of 16

Share Link: