CY7C1346H View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
CY7C1346H Datasheet PDF : 16 Pages
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CY7C1346H
Burst Sequences
The CY7C1346H provides a two-bit wraparound counter, fed
by A1, A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1, A0
00
Second
Address
A1, A0
01
Third
Address
A1, A0
10
01
00
11
10
11
00
11
10
01
Fourth
Address
A1, A0
11
10
01
00
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
tZZI
tRZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ Active to sleep current
ZZ Inactive to exit sleep current
Test Conditions
Min.
Max.
Unit
ZZ > VDD – 0.2V
40
mA
ZZ > VDD – 0.2V
2tCYC
ns
ZZ < 0.2V
2tCYC
ns
This parameter is sampled
2tCYC
ns
This parameter is sampled
0
ns
Document #: 38-05672 Rev. *B
Page 5 of 16
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