CY7C1325H View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

MFG CO.

CY7C1325H

4-Mbit (256 K × 18) Flow-Through Sync SRAM

Cypress Semiconductor 

CY7C1325H

Timing Diagrams (continued)

CLK

ADSP

tCYC

t

CH

tCL

tADS tADH

ADSC

ADDRESS

A1

tAS tAH

A2

BWE, BW [A:B]

CE

tCES tCEH

Figure 5. Read/Write Timing [19, 20, 21]

A3

A4

t

WES

t WEH

A5

A6

ADV

OE

Data In (D)

Data Out (Q)

High-Z

t

OEHZ

Q(A1)

Q(A2)

Back-to-Back READs

tDS tDH

D(A3)

Single WRITE

tOELZ

tCDV

Q(A4)

Q(A4+1) Q(A4+2)

BURST READ

DON’T CARE

UNDEFINED

Q(A4+3)

D(A5)

D(A6)

Back-to-Back

WRITEs

Notes

19. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.

20. The data bus (Q) remains in High Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.

21. GW is HIGH.

Document Number: 001-86114 Rev. **

Page 15 of 21

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