CY14B101I View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
CY14B101I Datasheet PDF : 42 Pages
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PRELIMINARY
CY14C101I
CY14B101I, CY14E101I
handbook, full pagewidth
SDA
MSB
Figure 4. Data Transfer on the I2C Bus
Acknowledgement
signal from slave
P
Acknowledgement Sr
signal from receiver
SCL
S
or
Sr
1
2
START or
Repeated START
condition
7
8
9
ACK
Byte complete,
interrupt within slave
1
2
3-8
9
ACK
Clock line held LOW while
interrupts are serviced
Sr
or
P
STOP or
Repeated START
condition
Byte Format
Each operation in I2C is done using 8-bit words. The bits are sent
in MSB first format on SDA line and each byte is followed by an
ACK signal by the receiver.
An operation continues till a NACK is sent by the receiver or
STOP or Repeated START condition is generated by the master
The SDA line must remain stable when the clock (SCL) is HIGH
except for a START or STOP condition.
Acknowledge /No-acknowledge
After transmitting one byte of data or address, the transmitter
releases the SDA line. The receiver pulls the SDA line LOW to
acknowledge the receipt of the byte. Every byte of data trans-
ferred on the I2C bus needs a response with an ACK signal by
the receiver to continue the operation. Failing to do so is
considered as a NACK state. NACK is the state where receiver
does not acknowledge the receipt of data and the operation is
aborted.
NACK can be generated by master during a READ operation in
following cases:
■ The master did not receive valid data due to noise.
■ The master generates a NACK to abort the READ sequence.
After a NACK is issued by the master, nvSRAM slave releases
control of the SDA pin and the master is free to generate a
Repeated START or STOP condition.
NACK can be generated by nvSRAM slave during a WRITE
operation in these cases:
■ nvSRAM did not receive valid data due to noise.
■ The master tries to access write protected locations on the
nvSRAM. Master must restart the communication by
generating a STOP or Repeated START condition.
Figure 5. Acknowledge on the I2C Bus
handbook, full pagewidth
DATA OUTPUT
BY MASTER
DATA OUTPUT
BY SLAVE
SCL FROM
MASTER
1
S
START
Condition
Not acknowledge (A)
Acknowledge (A)
2
8
9
Clock pulse for
acknowledgement
Document #: 001-54391 Rev. *C
Page 6 of 42
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