CY14B101K-SP25XIT View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

MFG CO.

CY14B101K-SP25XIT

1 Mbit (128K x 8) nvSRAM With Real Time Clock

Cypress Semiconductor 

Switching Waveforms

Figure 7 shows the SRAM Read Cycle 1(address controlled).[12, 13, 28]

Figure 7. SRAM Read Cycle 1

tRC

ADDRESS

DQ (DATA OUT)

tAA

tOHA

DATA VALID

CY14B101K

Figure 8 shows the SRAM Read Cycle 2 (CE and OE controlled).[12, 28]

Figure 8. SRAM Read Cycle 2

ADDRESS

CE

tRC

tLZCE

tACE

OE

DQ (DATA OUT)

ICC

tDOE

tLZOE

tPU

STANDBY

ACTIVE

tPD

tHZCE

tHZOE

DATA VALID

Note

28. HSB must remain HIGH during READ and WRITE cycles.

Document Number: 001-06401 Rev. *G

Page 18 of 24

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