CS8404A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS8404A Datasheet PDF : 33 Pages
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CS8403A CS8404A
Flag 2 is set high when byte 0 of the channel status,
address 08H, is read, and set low when byte 4, ad-
dress 0BH, is read. Therefore, flag 2 high indicates
the part is reading the first four bytes of channel
status and the last 20 bytes are free to update. If the
interrupt mask bit for flag 2 is set, the rising edge
will cause an interrupt indicating the beginning of
a channel status block as shown in Figure 11. Al-
though a falling edge on flag 0 and flag 1 may cause
an interrupt, the falling edge of flag 2 will not.
Figure 11 illustrates the flag timing for an entire
channel status block which includes 24 bytes of
channel status data and 384 audio samples. (This
figure assumes the channel status bit is the same for
the audio pair.) The lower portion of Figure 11 ex-
pands the first byte of channel status showing eight
pairs of data with a pair defined as a frame. This is
further expanded showing the first sub-frame (A0)
to contain 32 bits as per the AES/EBU specifica-
tions (see Appendix A). When transmitting stereo,
channel A is left and channel B is right. The pream-
ble at the bottom of Figure 11 is expanded in
Figure 15 to show the exact timing between flags,
the interrupt pin, and internal buffer-read timing.
Buffer Mode 0
In buffer mode 0, in addition to the user-data buffer
previously discussed, one entire block of channel
status data is buffered in 24 memory locations from
address 08H to 1FH. This block will be transmitted
Flag 2
Block
(384 Audio Samples)
Flag 1
Mode 0
Flag 1
Modes 1 & 2
Flag 0
23 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 0 1
Channel Status Byte
(Expanded)
Frame
A0 B0 A1 B1 A2 B2
(Expanded)
A7 B7
bit 0
34
78
Preamble Aux Data LSB
Sub-frame
Audio Data
27 28 29 30 31
MSB V U C P
Validity
See figure 15
User Data
Channel Status Data
Parity Bit
Figure 11. CS8403A Status Register Flag Timing
DS239PP1
13
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