CS18LV02565AAC-70 View Datasheet(PDF) - Unspecified

Part Name

Description

MFG CO.

CS18LV02565AAC-70

High Speed Super Low Power SRAM

Unspecified 

High Speed Super Low Power SRAM

32K-Word By 8 Bit

CS18LV02565

DC ELECTRICAL CHARACTERISTICS ( TA = 0o ~70oC, Vcc = 5.0V)

Name

Parameter

Test Condition

MIN TYP(1) MAX Unit

Guaranteed Input Low

VIL

Voltage (2)

Vcc=5.0V

-0.5

1.5

V

Guaranteed Input High

VIH

Voltage (2)

Vcc=5.0V

2.5

Vcc+0.2 V

IIL

Input Leakage Current

VCC=MAX, VIN=0 to VCC

-1

1

uA

VCC=MAX, /CE=VIN, or

IOL Output Leakage Current

-1

/OE=VIN , VIO=0V to VCC

1

uA

VOL Output Low Voltage

VCC=MAX, IOL = 1mA

0.4

V

VOH Output High Voltage

VCC=MIN, IOH = -1mA

2.2

V

Operating Power Supply

ICC

Current

/CE=VIL, IDQ=0mA,

F=FMAX =1/ tRC

20 mA

ICCSB TTL Standby Supply

ICCSB1 CMOS Standby Current

/CE=VIH, IDQ=0mA,

/CE≧VCC-0.2V, VIN≧

VCC-0.2V or VIN≦0.2V,

1

mA

1.0

4

uA

1. Typical characteristics are at TA = 25oC.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

DATA RETENTION CHARACTERISTICS ( TA = 0o ~70oC, Vcc = 5.0V )

Name

Parameter

Test Condition

MIN TYP(1) MAX

VCC for Data Retention

VDR

/CE ≧ VCC-0.2V, VIN ≧

1.5

VCC-0.2V or VIN≦0.2V

ICCDR

Data Retention Current

/CE≧VCC-0.2V, VIN≧

VCC-0.2V or VIN≦0.2V

0.5

3

TCDR

Chip Deselect to Data

Retention Time

tR

Operation Recovery Time

1. TA = 25oC.

Refer to

Retention Waveform

0

tRC (2)

2. tRC= .Read Cycle Time.

Unit

V

uA

ns

ns

6

Rev. 2.0

Chiplus reserves the right to change product or specification without notice.

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