Functional Block Diagram
Polarity
Blanking
Latch Enable
Data Input
Clock
Data Out
32-Bit
Shift
Register
Latch
Latch
Latch
Latch
HV5522/HV5530/HV5622/HV5630
HVOUT1
HVOUT2
(Outputs 3 to 30
not shown)
HVOUT31
HVOUT32
Function Table
Function
Data
CLK
Inputs
LE
BL
POL
All on
X
X
X
L
L
All off
X
X
X
L
H
Invert mode
X
X
L
H
L
Load S/R
Load
Latches
Transparent
Latch mode
H or L
↓
L
X
H or L
↑
X
H or L
↑
L
↓
H
H
↓
H
H
H
H
H
H
L
H
H
H
H
Notes:
H = high level, L = low level, X = irrelevant, ↓ = high-to-low transition, ↑ = low-to-high transistion.
* = dependent on previous stage’s state before the last CLK ↓ or last LE high.
Shift Reg
1 2…32
* *…*
* *…*
* *…*
H or L *…*
* *…*
* *…*
L *…*
H *…*
Outputs
HV Outputs
1 2…32
On On…On
Off Off…Off
*
*…*
*
*…*
*
*…*
*
*…*
Off *…*
On *…*
Data Out
*
*
*
*
*
*
*
*
*
4