PI6C39911 View Datasheet(PDF) - Pericom Semiconductor Corporation
Part Name
Description
MFG CO.
PI6C39911
Pericom Semiconductor Corporation
PI6C39911 Datasheet PDF : 11 Pages
| |||
PI6C39911/PI6C39912
1122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122
3.3V High Speed LVTTL or Balanced Output
Programmable Skew Clock Buffer-SuperClock®
Features
All output pair skew <100ps typical (250 Max.)
12.5 MHz to 135 MHz output operation
3.125 MHz to 135 MHz input operation
(input as low as 3.125 MHz for 4x operation, or
6.25 MHz for 2x operation)
User-selectable output functions
Selectable skew to 18ns
Inverted and non-inverted
Operation at ½ and ¼ input frequency
Operation at 2X and 4X input frequency
Zero input-to-output delay
50% duty-cycle outputs
LVTTL outputs drive 50-ohm terminated lines
Operates from a single 3.3V supply
Low operating current
32-pin PLCC package
Jitter < 200ps peak-to-peak (< 25ps RMS)
AvailableinLVTTL(PI6C39911)orBalanced(PI6C39912)
PI6C39911 is a pin-to-pin compatible with CY7B9911V
Description
The PI6C39911 and PI6C39912 offer selectable control over system
clock functions. These multiple-output clock drivers provide the
system integrator with functions necessary to optimize the timing
of high-performance computer systems. Eight individual drivers,
arranged as four pairs of user-controllable outputs, can each drive
terminated transmission lines with impedances as low as 50 ohms
while delivering minimal and specified output skews and full-swing
logic levels.
Each output can be hardwired to one of nine skews or function
configurations. Delay increments of 0.7ns to 1.5ns are determined
by the operating frequency with outputs able to skew up to ±6 time
units from their nominal zero skew position. The completely
integrated PLL allows external load and transmission line delay
effects to be canceled. The user can create output-to-output skew
of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems. When
combined with the internal PLL, these divide functions allow distri-
bution of a low-frequency clock that can be multiplied by two or four
at the clock destination. This feature allows flexibility and simpli-
fies system timing distribution design for complex high-speed
systems.
Logic Block Diagram
Test
FB
REF
Phase
Freq.
DET
Filter
VCO and
Time Unit
Generator
4F0
4F1
3F0
3F1
Select Inputs
(three level)
2F0
2F1
1F0
1F1
Skew
Select
Matrix
Pin Configuration
1Q0
1Q1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
3F1
4F0
4F1
VCCQ
VCCN
4Q1
4Q0
GND
GND
4 3 2 1 32 31 30
5
29
6
28
7
27
8
32 Pin
26
9
J
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
2F0
GND
1F1
1F0
VCCN
1Q0
1Q1
GND
GND
1
PS8497A 04/10/01
Share Link: 