AT88SC1003-10WI-00 View Datasheet(PDF) - Atmel Corporation

Part Name

Description

MFG CO.

AT88SC1003-10WI-00

1K EEPROM–Security Logic with Three Application Zones

Atmel Corporation 

Micro Operations

Table 8. Micro Operations

Operation

PGM

RESET

X

The AT88SC1003 circuit micro operation modes are selected by the input logic levels on

the control pins PGM, RST, and CLK and by the internal address. Timing for these oper-

ations is specified in Table 11 on page 19.

RST

CLK

0

Definition

The internal address is reset to “0”. After the falling edge of

RST, the first bit of the fabrication zone (Bit 0) will be driven

on the I/O contact. All erase flags (E1, E2, E3) are reset.

INC/READ

0

0

The address is incremented on the falling edge of CLK. If

read operations are enabled, the addressed bit will be

driven on the I/O contact after the falling edge of CLK. This

data is valid until the next falling edge of CLK, except for the

bits immediately preceding the security code and erase

keys. For these bits, the data is valid only while CLK is low.

When CLK goes high, the I/O line will be disabled (high

impedence). This will allow data to be set up on the I/O line

before comparing the first bit of each code. When read

operations are disabled, the I/O will be disabled and pulled

to a high state by the external system pullup resistor.

INC/CMP

0

0

The INC/CMP operation will compare the value of the data

driven by the system host on the I/O pin to the value of the

bit already written to the EEPROM memory at that address

location. This process is used during validation of the

AT88SC1003 security code and passwords. The data must

be stable on the I/O pin before the falling edge of CLK,

when the data will be latched internally. Comparison occurs

on the next falling edge of CLK. The address is

incremented on the falling edge of CLK.

ERASE/WRITE

1

0

The I/O pin must be driven to a “1” for an erase and to a “0”

for a write operation before the rising edge of CLK. CLK

must be held high for at least 2 ms. After the falling edge of

CLK, the data written to the EEPROM will be driven by the

AT88SC1003 on the I/O pin.

The device is placed in standby mode when FUS = “0” and

STANDBY

0

1

X

RST = “1”. The address counter will not increment when

RST is high.

Note:

The two instructions INC/READ and INC/CMP share the same control signal states. The circuit will distinguish between the two

instructions by testing the internal address counter. (CMP can only be done with the addresses corresponding to the security

code or to the erase keys.) The internal address counter counts up to 1599. An additional CLK pulse resets the address to “0”.

14 AT88SC1003

2035B–SMEM–08/03

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