AT26F004(2005) View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
AT26F004 Datasheet PDF : 37 Pages
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8. Program and Erase Commands
8.1 Byte Program
The Byte Program command allows a single byte of data to be programmed into a previously
erased memory location. An erased memory location is one that has all eight bits set to the logi-
cal “1” state (a byte value of FFh). Before a Byte Program command can be started, the Write
Enable command must have been previously issued to the device (see “Write Enable” on page
13) to set the Write Enable Latch (WEL) bit of the Status Register to a logical “1” state.
To perform a Byte Program command, an opcode of 02h must be clocked into the device fol-
lowed by the three address bytes denoting which byte location of the memory array to program.
After the address bytes have been clocked in, the next byte of data clocked into the device will
be latched internally. If more than one byte of data is clocked in, then only the first byte of data
sent on the SI pin will be stored in the internal latches and all subsequent bytes will be ignored.
When the CS pin is deasserted, the device will take the one byte stored in the internal latches
and program it into the memory array location specified by A23 - A0. The programming of the
byte is internally self-timed and should take place in a time of tBP. The three address bytes and a
complete byte of data must be clocked into the device before the CS pin is deasserted; other-
wise, the device will abort the operation and no data will be programmed into the memory array.
In addition, if the address specified by A23 - A0 points to a memory location within a sector that
is in the protected state (see “Protect Sector” on page 15), then the Byte Program command will
not be executed, and the device will return to the idle state once the CS pin has been deas-
serted. The WEL bit in the Status Register will be reset back to the logical “0” state if the
program cycle aborts due to an incomplete address being sent, an incomplete byte of data being
sent, or because the memory location to be programmed is protected.
While the device is programming, the Status Register can be read and will indicate that the
device is busy. For faster throughput, it is recommended that the Status Register be polled
rather than waiting the tBP time to determine if the byte has finished programming. At some point
before the program cycle completes, the WEL bit in the Status Register will be reset back to the
logical “0” state.
The Byte Program mode is the default programming mode after the device powers-up or
resumes from a device reset.
Figure 8-1. Byte Program
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12
29 30 31 32 33 34 35 36 37 38 39
OPCODE
ADDRESS BITS A23-A0
DATA IN
0 0 0 0 0 0 1 0AAAAAA
MSB
MSB
AAADDDDDDDD
MSB
HIGH-IMPEDANCE
8 AT26F004
3588A–DFLSH–10/05
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