APW7325 View Datasheet(PDF) - Anpec Electronics

Part Name

Description

MFG CO.

APW7325

5A 5V 1MHz Synchronous Buck Converter

Anpec Electronics 

APW7325

Application Information (Cont.)

Output Capacitor Selection (Cont.)

IL

ILIM

IPEAK

∆IL

IOUT

IP-FET

Layout Consideration

For all switching power supplies, the layout is an impor-

tant step in the design; especially at high peak currents

and switching frequencies. If the layout is not carefully

done, the regulator might show noise problems and duty

cycle jitter.

1. The input capacitor should be placed close to the PVDD

and GND. Connecting the capacitor and PVDD/GND

with short and wide trace without any via holes for good

input voltage filtering. The distance between VIN/GND

to capacitor less than 2mm respectively is

recommended.

2. To minimize copper trace connections that can inject

noise into the system, the inductor should be placed

as close as possible to the LX pin to minimize the

noise coupling into other circuits.

3. The output capacitor should be place closed to LX and

GND.

4. Since the feedback pin and network is a high imped-

ance circuit the feedback network should be routed

away from the inductor. The feedback pin and feed-

back network should be shielded with a ground plane

or trace to minimize noise coupling into this circuit.

5. A star ground connection or ground plane minimizes

ground shifts and noise is recommended.

Copyright © ANPEC Electronics Corp.

11

Rev. A.2 - Sep., 2013

0.6

8

7

6

5

3.45

1

2

1.25

3

4

Unit : mm

www.anpec.com.tw

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