The three D-channel loopback controls defined in
LMR2 bits 0, 1, and 2 are explained below:
Bit 0, D-channel loopback at Am79C30A/32A enable:
Bit 1, D-channel loopback at LIU enable:
Am79C30A
NT/PABX
DSD
Am79C30A
D
S
D
E
NT/PABX
D
D
This remote loopback is provided for maintenance pur-
poses from the NT’s perspective. The NT transmits
D-channel bits to the Am79C30A/32A where they are
internally looped (with the Data Link Controller) and
transmitted back to the NT. The incoming D-channel
data can be accessed by the microprocessor; however,
the microprocessor cannot send data on the outgoing
D channel.
Any difference between the transmitted D-channel bits
and the received E-channel bits to/from the
Am79C30A/32A (normally detected as an error which
halts the transmission) is ignored, thereby allowing the
transmission to continue.
MPI
This local loopback is provided for local testing. Data on
the incoming D channel is ignored. The data from the
microprocessor is processed by the DLC and then
looped back to the microprocessor.
Bit 2, D-channel back-off disable:
Am79C30A
D
S
E
NT/PABX
D
E
This loopback is provided for maintenance purposes
from the TE’s perspective. The Am79C30A/32A trans-
mits D-channel bits to the NT where they are looped
and transmitted back to the Am79C30A/32A in the E
channel. The operation is normal except differences
between the D and E channels do not halt the trans-
mission.
Multiframe Register (MF), Read/Write
Address = Indirect A6H
Table 14. Multiframe Register
Bit
Logical 1
Logical 0 (Default Value)
0
Enable Multiframe sync
Disable Multiframe sync
1
Enable S-data available interrupt
Disable interrupt
2
Enable Q-bit buffer empty interrupt
Disable interrupt
3
Enable Multiframe change of state interrupt
Disable interrupt
4
First subframe
Not first subframe
5, 6
Not used, reads logical 0
Not used, reads logical 0
7
Multiframe synchronized (read only)
Multiframe not synchronized (read only)
20
Am79C30A/32A Data Sheet