
PRELIMINARY
SWITCHING WAVEFORMS (continued)
CLK
TXD+
1
0
10
1
11
0
1
0 ETD
tTXTD
tTETD
TXD–
Figure 25. TP Ports Output Timing Diagram
20651B-30
tPWLP
tPERLP
Figure 26. TP Idle Link Test Pulse
20651B-31
VTSQ+
RXD+/–
VTSQ–
tPWKRD
tPWKRD
Figure 27. TP Receive Timing Diagram
tPWKRD
VTHS+
VTHS–
20560A-31
20651B-32
Am79C985
43