MCM64AF32SG15 View Datasheet(PDF) - Motorola => Freescale
Part Name
Description
MFG CO.
MCM64AF32SG15 Datasheet PDF : 12 Pages
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DATA RAMs WRITE CYCLE (CWE Controlled, See Notes 1 and 2)
–15
Parameter
Symbol
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
15
—
ns
3
Address Setup Time
Address Valid to End of Write
tAVWL
0
tAVWH
12
—
ns
—
ns
Write Pulse Width
tWLWH,
12
tWLEH
—
ns
Write Pulse Width, COE High
tWLWH,
10
tWLEH
—
ns
4
Data Valid to End of Write
tDVWH
7
—
ns
Data Hold Time
Write Low to Output High–Z
Write High to Output Active
tWHDX
0
tWLQZ
0
tWHQX
4
—
ns
7
ns
5, 6, 7
—
ns
5, 6, 7
Write Recovery Time
tWHAX
0
—
ns
NOTES:
1. A write occurs when CWE low.
2. If COE goes low coincident with or after CWE goes low, the output will remain in a high impedance state.
3. All timings are referenced from the last valid address to the first address transition.
4. If COE ≥ VIH, the output will remain in a high impedance state.
5. At any given voltage and temperature, tWLQZ max is less than tWHQX min, both for a given device and from device to device.
6. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B.
7. This parameter is sampled and not 100% tested.
DATA RAMs WRITE CYCLE (CALE ≥ VIH) (CWE Controlled, See Notes 1 and 2)
A5 – A17
CAAx, CABx
(CACHE ADDRESS A/B)
CWEx (WRITE ENABLE)
D (DATA IN)
Q (DATA OUT)
tAVAV
tAVWL
HIGH–Z
tWLQZ
tAVWH
tWLEH
tWLWH
tDVWH
DATA VALID
HIGH–Z
tWHAX
tWHDX
tWHQX
MCM64AF32
8
MOTOROLA FAST SRAM
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