ADT7516ARQ-REEL(RevA) View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
ADT7516ARQ-REEL
(Rev.:RevA)
(Rev.:RevA)
Analog Devices
ADT7516ARQ-REEL Datasheet PDF : 44 Pages
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AIN3 VLOW Limit Register (Read/Write) [Add. = 2Eh]
This limit register is an 8-bit read/write register that stores the
AIN3 input lower limit, which will cause an interrupt and
activate the INT/INT output (if enabled). For this to happen,
the measured AIN3 value has to be less than or equal to the
value in this register. Because it is an 8-bit register, the reso-
lution is four times less than the resolution of the 10-bit ADC.
The default value is 0 V.
Table 64. AIN3 VLOW Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0* 0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
AIN4 VHIGH Limit Register (Read/Write) [Add. = 2Fh]
This limit register is an 8-bit read/write register that stores the
AIN4 input upper limit, which will cause an interrupt and acti-
vate the INT/INT output (if enabled). For this to happen, the
measured AIN4 value has to be greater than the value in this
register. Because it is an 8-bit register, the resolution is four
times less than the resolution of the 10-bit ADC. The default
value is full-scale voltage.
Table 65. AIN4 VHIGH Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1* 1* 1* 1* 1* 1* 1* 1*
*Default settings at power-up.
AIN4 VLOW Limit Register (Read/Write) [Add. = 30h]
This limit register is an 8-bit read/write register that stores the
AIN4 input lower limit, which will cause an interrupt and
activate the INT/INT output (if enabled). For this to happen,
the measured AIN4 value has to be less than or equal to the
value in this register. Because it is an 8-bit register, the reso-
lution is four times less than the resolution of the 10-bit ADC.
The default value is 0 V.
Table 66. AIN4 VLOW Limit
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0* 0* 0* 0* 0* 0* 0* 0*
*Default settings at power-up.
Device ID Register (Read-Only) [Add. = 4Dh]
This 8-bit read-only register indicates which part the device is
in the model range. ADT7516 = 03h, ADT7517 = 07h, and
ADT7519 = 0Bh.
Manufacturer’s ID Register (Read-Only) [Add. = 4Eh]
This register contains the manufacturer’s identification number.
ADI’s ID number is 41h.
ADT7516/ADT7517/ADT7519
Silicon Revision Register (Read-Only) [Add. = 4Fh]
This register is divided into the four LSBs representing the
stepping and the four MSBs representing the version. The
stepping contains the manufacturer’s code for minor revisions
or steppings to the silicon. The version is the ADT7516/
ADT7517/ADT7519 version number.
SPI Lock Status Register (Read-Only) [Add. = 7Fh]
Bit D0 (LSB) of this read-only register indicates whether or not
the SPI interface is locked. Writing to this register will cause the
device to malfunction. The default value is 00h.
0 = I2C interface.
1 = SPI interface selected and locked.
SERIAL INTERFACE
There are two serial interfaces that can be used on this part: I2C
and SPI. The device will power up with the serial interface in
I2C mode, but it is not locked into this mode. To stay in I2C
mode, it is recommended that the user tie the CS line to either
VCC or GND. It is not possible to lock the I2C mode, but it is
possible to select and lock the SPI mode.
To select and lock the interface into the SPI mode, a number of
pulses must be sent down the CS line (Pin 4). The following
section describes how this is done.
Once the SPI communication protocol has been locked in, it
cannot be unlocked while the device is still powered up. Bit D0
of the SPI lock status register (Address 7Fh) is set to 1 when a
successful SPI interface lock has been accomplished. To reset
the serial interface, the user must power down the part and
power it up again. A software reset does not reset the serial
interface.
Serial Interface Selection
The CS line controls the selection between I2C and SPI.
Figure 59 shows the selection process necessary to lock the SPI
interface mode.
To communicate to the ADT7516/ADT7517/ADT7519 using
the SPI protocol, send three pulses down the CS line as shown
in Figure 59. On the third rising edge (marked as C in
Figure 59), the part selects and locks the SPI interface. The user
is now limited to communicating to the device using the SPI
protocol.
As per most SPI standards, the CS line must be low during
every SPI communication to the ADT7516/ADT7517/
ADT7519 and high all other times. Typical examples of how to
connect the dual interface as I2C or SPI is shown in Figure 57
and Figure 58. The following sections describe in detail how to
use the I2C and SPI protocols associated with the ADT7516/
ADT7517/ADT7519.
Rev. A | Page 37 of 44
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