AD9851(RevC) View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

AD9851
(Rev.:RevC)

CMOS 180 MHz DDS/DAC Synthesizer

Analog Devices 

AD9851

Rx

RF IN

VCA

I

I/Q MIXER

AND

LOW PASS Q

FILTER

AD9059

DUAL

8-BIT ADC

8

DIGITAL

8

DEMODULATOR

ADC CLOCK FREQUENCY

LOCKED TO

Tx CHIP/SYMBOL/PN RATE

ADC ENCODE

180MHz

OR 30MHz

REFERENCE

CLOCK

AD9851

CLOCK

GENERATOR

32

CHIP/SYMBOL /PN

RATE DATA

AGC

Rx BASEBAND

DIGITAL DATA OUT

Figure 1. “Chip Rate” Clock Generator Application in a Spread Spectrum Receiver

IOUT

MICROPROCESSOR

OR

MICROCONTROLLER

DATA

BUS

8-BIT PARALLEL DATA,

OR 1-BIT ؋ 40 SERIAL DATA,

RESET, W CLK AND FQ UD

IOUTB

180MHz OR 30MHz

REFERENCE

CLOCK

AD9851

RSET

CMOS

OUTPUTS

QOUT

QOUTB

3.9k⍀

470pF 100k⍀

100k⍀

100⍀

LOW-PASS

FILTER

200⍀

7TH ORDER ELLIPTICAL

70MHz LOW PASS

200⍀ IMPEDANCE

200⍀

VOLTAGE HERE = CENTER POINT

OF SINE WAVE (0.5V TYPICALLY)

USING PASSIVE "AVERAGING" CIRCUIT

0 TO 1V p-p

SINE WAVE

Figure 2. Basic Clock Generator Configuration

Both IOUT and IOUTB are equally loaded with 100 Ω. Two

100 kΩ resistors “sample” each output and average the two

voltages. The result is filtered with the 470 pF capacitor and

applied to one comparator input as a dc switching threshold.

The filtered DAC sine wave output is applied to the other com-

parator input. The comparator will toggle with nearly 50% duty

cycle as the sine wave alternately traverses the “center point”

threshold.

IF FREQUENCY

IN

FILTER

RF

FREQUENCY

OUT

REFERENCE

CLOCK

FILTER

AD9851

DDS

TUNING

WORD

Figure 3. Frequency/Phase-Agile Local Oscillator for

Frequency Mixing/Multiplying

REFERENCE

CLOCK

AD9851

DDS

TUNING

WORD

FILTER

PHASE

COMPARATOR

LOOP

FILTER

VCO

RF

FREQUENCY

OUT

DIVIDE-BY-N

Figure 4. Frequency/Phase-Agile Reference for PLL

REFERENCE

CLOCK

PHASE

COMPARATOR

LOOP

FILTER

VCO

RF

FREQUENCY

OUT

FILTER

AD9851

DDS

TUNING

WORD

REF CLK IN

PROGRAMMABLE

"DIVIDE-BY-N" FUNCTION

(WHERE N = 232/TUNING WORD)

Figure 5. Digitally-Programmable “Divide-by-N” Function

in PLL

EZ-KIT LITE

DSP

ADSP-2181

DSP

PROCESSOR

L&R

AUDIO IN

AD1847

STEREO

CODEC

ADSP-2181

BUS

8-BIT

DATA

BUS

INPUT/

OUTPUT

DECODE

LOGIC

AD9851/FSPCB

EVALUATION

BOARD

DAC

OUT

AD9851

DDS

REF

OSC

FM RF

OUTPUT

Figure 6. High Quality, All-Digital RF Frequency Modulation

High quality, all digital RF frequency modulation generation

with the ADSP-2181 DSP and the AD9851 DDS. This applica-

tion is well documented in Analog Devices’ application Note

AN-543, and uses an “image” of the DDS output as illustrated

in Figure 8.

–6–

REV. C

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