AD9629-20(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD9629-20
(Rev.:Rev0)
(Rev.:Rev0)
Analog Devices
AD9629-20 Datasheet PDF : 32 Pages
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Clock Duty Cycle
Typical high speed ADCs use both clock edges to generate
a variety of internal timing signals and, as a result, may be
sensitive to clock duty cycle. Commonly, a 50% duty cycle clock
with ±5% tolerance is required to maintain optimum dynamic
performance as shown in Figure 51.
Jitter on the rising edge of the clock input can also impact dynamic
performance and should be minimized as discussed in the Jitter
Considerations section.
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75
70
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60
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50
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40
10
20
30
40
50
60
70
80
POSITIVE DUTY CYCLE (%)
Figure 51. SNR vs. Clock Duty Cycle
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low fre-
quency SNR (SNRLF) at a given input frequency (fINPUT) due to
jitter (tJRMS) can be calculated by
SNRHF = −10 log[(2π × fINPUT × tJRMS)2 + 10 (−SNRLF /10) ]
In the previous equation, the rms aperture jitter represents the
clock input jitter specification. IF undersampling applications
are particularly sensitive to jitter, as illustrated in Figure 52.
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0.05ps
70
0.2ps
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60
0.5ps
55
1.0ps
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1.5ps
2.0ps
45
3.0ps 2.5ps
1
10
100
1k
FREQUENCY (MHz)
Figure 52. SNR vs. Input Frequency and Jitter
AD9629
The clock input should be treated as an analog signal in cases in
which aperture jitter may affect the dynamic range of the AD9629.
To avoid modulating the clock signal with digital noise, keep
power supplies for clock drivers separate from the ADC output
driver supplies. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
For more information, see the AN-501 Application Note and the
AN-756 Application Note available on www.analog.com.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 53, the analog core power dissipated by
the AD9629 is proportional to its sample rate. The digital
power dissipation of the CMOS outputs are determined
primarily by the strength of the digital drivers and the load
on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits (13, in the case of the
AD9629).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of fCLK/2. In practice, the DRVDD current is estab-
lished by the average number of output bits switching, which
is determined by the sample rate and the characteristics of the
analog input signal.
Reducing the capacitive load presented to the output drivers
can minimize digital power consumption. The data in Figure 53
was taken using the same operating conditions as those used for
the Typical Performance Characteristics, with a 5 pF load on
each output driver.
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AD9231-80
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65
AD9231-65
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50
AD9231-40
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40
AD9231-20
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CLOCK RATE (MSPS)
Figure 53. Analog Core Power vs. Clock Rate
Rev. 0 | Page 21 of 32
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