AD9629-20(Rev0) View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

AD9629-20
(Rev.:Rev0)

12-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter

Analog Devices 

AD9629

CLOCK INPUT CONSIDERATIONS

For optimum performance, clock the AD9629 sample clock inputs,

CLK+ and CLK−, with a differential signal. The signal is typi-

cally ac-coupled into the CLK+ and CLK− pins via a transformer

or capacitors. These pins are biased internally (see Figure 45)

and require no external bias.

AVDD

CLK+

2pF

0.9V

CLK–

2pF

Figure 45. Equivalent Clock Input Circuit

Clock Input Options

The AD9629 has a very flexible clock input structure. The clock

input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal being used, clock source jitter is

of great concern, as described in the Jitter Considerations section.

Figure 46 and Figure 47 show two preferred methods for clock-

ing the AD9629. The CLK inputs support up to 4× the rated

sample rate when using the internal clock divider feature. A low

jitter clock source is converted from a single-ended signal to a

differential signal using either an RF transformer or an RF balun.

CLOCK

INPUT

0.1µF

Mini-Circuits®

ADT1-1WT, 1:1 Z

XFMR 0.1µF

50Ω 100Ω

0.1µF

0.1µF

SCHOTTKY

DIODES:

HSMS2822

CLK+

ADC

CLK–

Figure 46. Transformer-Coupled Differential Clock (3 MHz to 200 MHz)

CLOCK

INPUT

1nF

50Ω

1nF

0.1µF

0.1µF

SCHOTTKY

DIODES:

HSMS2822

CLK+

ADC

CLK–

Figure 47. Balun-Coupled Differential Clock (Up to 4× Rated Sample Rate)

The RF balun configuration is recommended for clock frequencies

between 80 MHz and 320 MHz, and the RF transformer is recom-

mended for clock frequencies from 3 MHz to 200 MHz. The

back-to-back Schottky diodes across the transformer/balun

secondary limit clock excursions into the AD9629 to ~0.8 V p-p

differential.

This limit helps prevent the large voltage swings of the clock

from feeding through to other portions of the AD9629 while

preserving the fast rise and fall times of the signal that are critical

to a low jitter performance.

If a low jitter clock source is not available, another option is to

ac couple a differential PECL signal to the sample clock input

pins, as shown in Figure 48. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515/AD9516/AD9517 clock drivers

offer excellent jitter performance.

CLOCK

INPUT

CLOCK

INPUT

50kΩ

0.1µF

AD951x

0.1µF PECL DRIVER

50kΩ

240Ω

0.1µF

100Ω

0.1µF

240Ω

CLK+

ADC

CLK–

Figure 48. Differential PECL Sample Clock (Up to 4× Rated Sample Rate)

A third option is to ac couple a differential LVDS signal to the

sample clock input pins, as shown in Figure 49. The AD9510/

AD9511/AD9512/AD9513/AD9514/AD9515/AD9516/AD9517

clock drivers offer excellent jitter performance.

CLOCK

INPUT

CLOCK

INPUT

50kΩ

0.1µF

AD951x

0.1µF LVDS DRIVER

50kΩ

0.1µF

100Ω

0.1µF

CLK+

ADC

CLK–

Figure 49. Differential LVDS Sample Clock (Up to 4× Rated Sample Rate)

In some applications, it may be acceptable to drive the sample

clock inputs with a single-ended 1.8 V CMOS signal. In such

applications, drive the CLK+ pin directly from a CMOS gate, and

bypass the CLK− pin to ground with a 0.1 μF capacitor (see

Figure 50).

CLOCK

INPUT

VCC

0.1µF 1kΩ

50Ω1

1kΩ

AD951x

CMOS DRIVER

OPTIONAL

100Ω

0.1µF

CLK+

ADC

0.1µF

CLK–

150Ω RESISTOR IS OPTIONAL.

Figure 50. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)

Input Clock Divider

The AD9629 contains an input clock divider with the ability

to divide the input clock by integer values of 1, 2, or 4.

Rev. 0 | Page 20 of 32

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