AD9628(Rev0) View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD9628 Datasheet PDF : 44 Pages
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
CLK+ 1
CLK– 2
SYNC 3
NC 4
NC 5
NC 6
NC 7
D0B (LSB) 8
D1B 9
DRVDD 10
D2B 11
D3B 12
D4B 13
D5B 14
D6B 15
D7B 16
PIN 1
INDICATOR
AD9628
PARALLEL CMOS
TOP VIEW
(Not to Scale)
48 PDWN
47 OEB
46 CSB
45 SCLK/DFS
44 SDIO/DCS
43 ORA
42 D11A (MSB)
41 D10A
40 D9A
39 D8A
38 D7A
37 DRVDD
36 D6A
35 D5A
34 D4A
33 D3A
AD9628
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES
THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 6. Parallel CMOS Pin Configuration (Top View)
Table 8. Pin Function Descriptions (Parallel CMOS Mode)
Pin No.
Mnemonic
Type
Description
ADC Power Supplies
10, 19, 28, 37
DRVDD
Supply
Digital Output Driver Supply (1.8 V Nominal).
49, 50, 53, 54,
59, 60, 63, 64
AVDD
Supply
Analog Power Supply (1.8 V Nominal).
4, 5, 6, 7, 25, 26, NC
27, 29
No Connect. Do not connect to these pins.
0
AGND,
Ground
The exposed thermal pad on the bottom of the package provides the analog
Exposed Pad
ground for the part. This exposed pad must be connected to ground for proper
operation.
ADC Analog
51
VIN+A
Input
Differential Analog Input Pin (+) for Channel A.
52
VIN−A
Input
Differential Analog Input Pin (−) for Channel A.
62
VIN+B
Input
Differential Analog Input Pin (+) for Channel B.
61
VIN−B
Input
Differential Analog Input Pin (−) for Channel B.
55
VREF
Input/Output Voltage Reference Input/Output.
56
SENSE
Input
Reference Mode Selection.
58
RBIAS
Input/Output External Reference Bias Resistor.
57
VCM
Output
Common-Mode Level Bias Output for Analog Inputs.
1
CLK+
Input
ADC Clock Input—True.
2
CLK−
Input
ADC Clock Input—Complement.
Digital Input
3
SYNC
Input
Digital Synchronization Pin. Slave mode only.
Rev. 0 | Page 13 of 44
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