Pin No.
33
34
38
39
40
41
43
44
46
47
49
50
52
53
54
55
56
57
58
60
61
63
64
Mnemonic
D−A
D+A
SCLK/DTP
SDIO/ODM
CSB
PDWN
VIN+A
VIN−A
VIN−B
VIN+B
VIN+C
VIN−C
VIN−D
VIN+D
RBIAS
SENSE
VREF
REFB
REFT
VIN+E
VIN−E
VIN−F
VIN+F
Description
ADC A Digital Output—Complement
ADC A True Digital Output—True
Serial Clock/Digital Test Pattern
Serial Data Input-Output/Output Driver Mode
Chip Select Bar
Power Down
ADC A Analog Input—True
ADC A Analog Input—Complement
ADC B Analog Input—Complement
ADC B Analog Input—True
ADC C Analog Input—True
ADC C Analog Input—Complement
ADC D Analog Input—Complement
ADC D Analog Input—True
External Resistor to Set the Internal ADC Core Bias Current
Reference Mode Selection
Voltage Reference Input/Output
Differential Reference (Negative)
Differential Reference (Positive)
ADC E Analog Input—True
ADC E Analog Input—Complement
ADC F Analog Input—Complement
ADC F Analog Input—True
AD9212
Rev. 0 | Page 11 of 56