100
TA = +25°C
ALL DIGITAL INPUTS
10
TIED TOGETHER
1.0
VDD = +5V
0.1
0.01
0.001
VDD = +3V
0.0001
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
INPUT VOLTAGE – Volts
Figure 7. Supply Current vs. Logic Input Voltage
80
60
VDD = +5V
ALL OUTPUTS SET
TO MIDSCALE (80H)
40
20
0
10
100
1k
10k
100k
FREQUENCY – Hz
Figure 8. Power Supply Rejection vs. Frequency
2V
6V
100
4V 90
OUT
2V
0V
5V 10
CS
0%
0V 0%
5V
5µs
VDD = +5V
VREF = +5V
TIME – 5µs/DIV
Figure 9. Large-Signal Settling Time
AD8802/AD8804
OUTPUT1: OOH → FFH
VDD = +5V
100
90
VREF = +5V
f = 1MHz
10
0%
10mV
200ns
TIME – 0.2µs/DIV
Figure 10. Adjacent Channel Clock Feedthrough
100
90
OUT1
5mV/DIV
CS
5V/DIV 10
0%
5mV
1µs
OUTPUT1: 7FH → 80H
VDD = +5V
VREF = +5V
5V
TIME – 1µs/DIV
Figure 11. Midscale Transition
0.01
0.005
VDD = +4.5V
VREF = +4.5V
SS = 176 PCS
VREFL = 0V
0
–0.005
–0.01
0
100
200
300
400
500
600
HOURS OF OPERATION AT 150°C
Figure 12. Zero-Scale Error Accelerated by Burn-In
REV. 0
–5–