AD7798BRU View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD7798BRU Datasheet PDF : 28 Pages
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AD7798/AD7799
0
–10
–20
–30
–40
–50
–60
0
1000 2000 3000 4000 5000 6000 700 8000 9000 10000
FREQUENCY (Hz)
Figure 16. Filter Response at 500 Hz Update Rate
DIGITAL INTERFACE
As previously outlined, the AD7798/AD7799’s programmable
functions are controlled using a set of on-chip registers. Data is
written to these registers via the part’s serial interface and read
access to the on-chip registers is also provided by this interface.
All communications with the part must start with a write to the
communications register. After power-on or reset, the device
expects a write to its communications register. The data written
to this register determines whether the next operation is a read
operation or a write operation and also determines to which
register this read or write operation occurs. Therefore, write
access to any of the other registers on the part begins with a
write operation to the communications register followed by a
write to the selected register. A read operation from any other
register (except when continuous read mode is selected) starts
with a write to the communications register followed by a read
operation from the selected register.
The AD7798/AD7799’s serial interface consists of four signals:
CS, DIN, SCLK, and DOUT/RDY. The DIN line is used to
transfer data into the on-chip registers while DOUT/RDY is
used for accessing from the on-chip registers. SCLK is the serial
clock input for the device and all data transfers (either on DIN
or DOUT/RDY) occur with respect to the SCLK signal. The
DOUT/ RDY pin operates as a data ready signal also, the line
going low when a new data-word is available in the output
register. It is reset high when a read operation from the data
register is complete. It also goes high prior to the updating of
the data register to indicate when not to read from the device, to
ensure that a data read is not attempted while the register is
being updated. CS is used to select a device. It can be used to
decode the AD7798/AD7799 in systems where several
components are connected to the serial bus.
Preliminary Technical Information
Figure 3 and Figure 4 show timing diagrams for interfacing to
the AD7798/AD7799 with CS being used to decode the part.
Figure 3 shows the timing for a read operation from the
AD7798/AD7799’s output shift register while Figure 4 shows
the timing for a write operation to the input shift register. It is
possible to read the same word from the data register several
times even though the DOUT/RDY line returns high after the
first read operation. However, care must be taken to ensure that
the read operations have been completed before the next output
update occurs. In continuous read mode, the data register can
be read only once.
The serial interface can operate in 3-wire mode by tying CS low.
In this case, the SCLK, DIN, and DOUT/RDY lines are used to
communicate with the AD7798/AD7799. The end of the con-
version can be monitored using the RDY bit in the status regis-
ter. This scheme is suitable for interfacing to micro-controllers.
If CS is required as a decoding signal, it can be generated from a
port pin. For microcontroller interfaces, it is recommended that
SCLK idles high between data transfers.
The AD7798/AD7799 can be operated with CS being used as a
frame synchronization signal. This scheme is useful for DSP
interfaces. In this case, the first bit (MSB) is effectively clocked
out by CS since CS would normally occur after the falling edge
of SCLK in DSPs. The SCLK can continue to run between data
transfers, provided the timing numbers are obeyed.
The serial interface can be reset by writing a series of 1s on the
DIN input. If a Logic 1 is written to the AD7798/AD7799 line
for at least 32 serial clock cycles, the serial interface is reset. This
ensures that the interface can be reset to a known state if the
interface gets lost due to a software error or some glitch in the
system. Reset returns the interface to the state in which it is
expecting a write to the communications register. This opera-
tion resets the contents of all registers to their power-on values.
Following a reset, the user should allow a period of 500 s before
addressing the serial interface.
The AD7798/AD7799 can be configured to continuously
convert or to perform a single conversion. See Figure 17
through Figure 19.
Pr.E 10/04 | Page 20 of 28
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