AD7764BRUZ-REEL7 View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

AD7764BRUZ-REEL7

24-Bit, 312 kSPS, 109 dB Σ-Δ ADC with On-Chip Buffers and Serial Interface

Analog Devices 

AD7764

Pin No.

14

15

16

19

18

Mnemonic

FSI

SYNC

RESET/

PWRDWN

MCLK

DEC_RATE

Description

Frame Sync Input. The status of this pin is checked on the falling edge of SCO. If this pin is low, then the first

data bit is latched in on the next SCO falling edge. See the AD7764 Interface section for further details.

Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize

multiple devices in a system. See the Synchronization section for further details.

Reset/Power-down Pin. When a logic low is sensed on this pin, the part is powered down and all internal

circuitry is reset.

Master Clock Input. A low jitter digital clock must be applied to this pin. The output data rate depends on the

frequency of this clock. See the Clocking the AD7764 section for more details.

Decimation Rate. This pin selects one of the three decimation rate modes. When 2.5 V is applied to this pin,

a decimation rate 64× is selected. A decimation rate of 128× is selected by leaving the pin floating. A

decimation rate of 256× is selected by setting the pin to ground.

Rev. 0 | Page 10 of 32

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