AD7747ARUZ-REEL7 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD7747ARUZ-REEL7 Datasheet PDF : 28 Pages
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AD7747
TIMING SPECIFICATIONS
VDD = 2.7 V to 3.6 V, or 4.75 V to 5.25 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
SERIAL INTERFACE1, 2
SCL Frequency
SCL High Pulse Width, tHIGH
SCL Low Pulse Width, tLOW
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Hold Time (Start Condition), tHD;STA
Setup Time (Start Condition), tSU;STA
Data Setup Time, tSU;DAT
Setup Time (Stop Condition), tSU;STO
Data Hold Time, tHD;DAT (Master)
Bus-Free Time (Between Stop and Start Condition, tBUF)
Min Typ Max Unit
0
400 kHz
0.6
μs
1.3
μs
0.3 μs
0.3 μs
0.6
μs
0.6
μs
0.1
μs
0.6
μs
0
μs
1.3
μs
Test Conditions/Comments
See Figure 2
After this period, the first clock is generated
Relevant for repeated start condition
1 Sample tested during initial release to ensure compliance.
2 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs.
Output load = 10 pF.
SCL
tR
tLOW
SDA
tBUF
P
S
tHD;STA
tHD;DAT
tF
tHIGH
tSU;DAT
tHD;STA
tSU;STA
S
Figure 2. Serial Interface Timing Diagram
tSU;STO
P
Rev. 0 | Page 5 of 28
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