AD7623ASTZRL View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD7623ASTZRL Datasheet PDF : 28 Pages
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AD7623
TIMING SPECIFICATIONS
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
CONVERSION AND RESET (Refer to Figure 31 and Figure 32)
Convert Pulse Width
Time Between Conversions
CNVST Low to BUSY High Delay
BUSY High All Modes (Except Master Serial Read After Convert)
Aperture Delay
End of Conversion to BUSY Low Delay
Conversion Time
Acquisition Time
RESET Pulse Width
RESET Low to BUSY High Delay2
BUSY High Time from RESET Low2
PARALLEL INTERFACE MODES (Refer to Figure 33 to Figure 35).
CNVST Low to DATA Valid Delay
DATA Valid to BUSY Low Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
MASTER SERIAL INTERFACE MODES3 (Refer to Figure 37 and Figure 38)
CS Low to SYNC Valid Delay
CS Low to Internal SCLK Valid Delay3
CS Low to SDOUT Delay
CNVST Low to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period4
Internal SCLK High4
Internal SCLK Low4
SDOUT Valid Setup Time4
SDOUT Valid Hold Time4
SCLK Last Edge to SYNC Delay4
CS High to SYNC HI-Z
CS High to Internal SCLK HI-Z
CS High to SDOUT HI-Z
BUSY High in Master Serial Read after Convert4
CNVST Low to SYNC Asserted Delay
SYNC Deasserted to BUSY Low Delay
SLAVE SERIAL INTERFACE MODES3 (Refer to Figure 40 and Figure 41)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK High
External SCLK Low
Symbol Min
t1
15
t2
750
t3
t4
t5
t6
10
t7
t8
125
t9
15
t38
t39
t10
t11
2
t12
t13
2
t14
t15
t16
t17
t18
0.5
t19
8
t20
2
t21
3
t22
1
t23
0
t24
0
t25
t26
t27
t28
t29
t30
t31
5
t32
1
t33
5
t34
5
t35
12.5
t36
5
t37
5
Typ
Max
701
23
560
1
560
10
600
560
20
15
10
10
10
263
12
10
10
10
See Table 4
500
13
8
1 See the Conversion Control section.
2 See the Digital Interface and RESET sections.
3 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
4 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev. 0 | Page 5 of 28
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