AD7398BR-REEL7 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD7398BR-REEL7 Datasheet PDF : 16 Pages
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AD7398/AD7399
AD7399 10-BIT VOLTAGE OUTPUT DAC (@ VDD = 5 V, VSS = 0 V; or VDD = +5 V, VSS = –5 V, VREF = +2.5 V, –40؇C < TA
< +125؇C, unless otherwise noted.)
Parameter
Symbol Condition
3 V–5 V ؎ 10% ؎5 V ؎ 10% Unit
STATIC PERFORMANCE
Resolution1
Relative Accuracy2
Differential Nonlinearity2
Zero-Scale Error
Full-Scale Voltage Error
Full-Scale Tempco3
N
INL
DNL
VZSE
VFSE
TCVFS
Monotonic
Data = 000H
Data = 3FFH
10
10
Bits
±1
±1
LSB max
±1
±1
LSB max
7
±4
mV max
± 15
± 15
mV max
1.5
1.5
ppm/°C typ
REFERENCE INPUT
VREFIN Range4
Input Resistance5
Input Capacitance3
VREF
RREF
CREF
Data = 155H, Worst-Case
0/VDD
40
5
VSS/VDD
40
5
V min/max
kΩ typ6
pF typ
ANALOG OUTPUT
Output Current
Capacitive Load3
IOUT
CL
Data = 200H, ∆VOUT = 1 LSB
No Oscillation
200
±5
mA typ
400
pF max
LOGIC INPUTS
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance3
INTERFACE TIMING3, 7
Clock Frequency
Clock Width High
Clock Width Low
CS to Clock Set Up
Clock to CS Hold
Load DAC Pulsewidth
Data Setup
Data Hold
Load Setup to CS
Load Hold to CS
VIL
VIH
IIL
CIL
fCLK
tCH
tCL
tCSS
tCSH
tLDAC
tDS
tDH
tLDS
tLDH
VDD = 3 V
VDD = 5 V
CLK Only
0.5
0.8
0.8
80% VDD
4.0
2.1–2.4
2.4
1
1
10
10
11
16.6
45
30
45
30
10
5
20
15
45
30
15
10
10
5
0
0
20
15
V max
V max
V min
V min
µA max
pF max
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
AC CHARACTERISTICS
Output Slew Rate
Settling Time8
Shutdown Recovery
DAC Glitch
Digital Feedthrough
Feedthrough
SR
Data = 000H to 3FFH to 000H
2
tS
To ± 0.1% of Full Scale
6
tSDR
6
Q
Code 1FFH to 200H to 1FFH
150
QDF
15
VOUT/VREF VREF = 1.5 VDC + 1 V p-p,
–63
Data = 000H, f = 100 kHz
2
V/µs typ
6
µs typ
6
µs typ
150
nVs typ
15
nVs typ
–63
dB typ
SUPPLY CHARACTERISTICS
Shutdown Supply Current
Positive Supply Current
Negative Supply Current
Power Dissipation
Power Supply Sensitivity
IDD_SD
IDD
ISS
PDISS
PSS
No Load
VIL = 0 V, No Load
VIL = 0 V, No Load
VIL = 0 V, No Load
∆VDD = ± 5%
30/60
1.5/2.5
1.5/2.5
5
0.006
30/60
1.6/2.7
1.6/2.7
16
0.006
µA typ/max
mA typ/max
mA typ/max
mW typ
%/% max
NOTES
1One LSB = VREF/1024 V for the 10-bit AD7399.
2The first two codes (000H, 001H) are excluded from the linearity error measurement in single supply operation.
3These parameters are guaranteed by design and not subject to production testing.
4When VREF is connected to either the VDD or the VSS power supply the corresponding VOUT voltage will program between ground and the supply voltage minus the
offset voltage of the output buffer, which is the same as the VZSE error specification. See additional discussion in the Operation section of the data sheet.
5Input resistance is code-dependent.
6Typicals represent average readings measured at 25°C.
7All input control signals are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
8The settling time specification does not apply for negative going transitions within the last 3 LSBs of ground.
Specifications subject to change without notice.
REV. 0
–3–
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