AD7091 View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD7091 Datasheet PDF : 20 Pages
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AD7091
BUSY INDICATOR DISABLED
To operate the AD7091 without the busy indicator, a conversion
must first be started. A high-to-low transition on CONVST initi-
ates a conversion. This transition places the track-and-hold into
hold mode and samples the analog input at this point. If the user
does not want the AD7091 to enter power-down mode, CONVST
should be taken high before the end of the conversion.
A conversion requires 650 ns to complete. When the conversion
process is finished, the track-and-hold returns to track mode. To
prevent the busy indicator from becoming enabled, ensure that
CS is pulled high before the end of the conversion (see Figure 27).
Data Sheet
The conversion result is shifted out of the device as a 12-bit
word under the control of SCLK and CS. The MSB (Bit DB11)
is clocked out on the falling edge of CS. DB10 to DB0 are shifted
out on the subsequent falling edges of SCLK. The 12th SCLK
falling edge returns SDO to a high impedance state. After all the
data is clocked out, pull CS high again. Data is propagated on
SCLK falling edges and is valid on both the rising and falling
edges of the next SCLK. The timing diagram for this operation
is shown in Figure 27.
If another conversion is required, pull CONVST low again and
repeat the cycle.
EOC
t7
CONVST
t8
t12
CS
t11
SCLK
SDO
t10
THREE-STATE
1
2
DB11
t2
DB10
3
DB9
4
DB8
t3
5
t4
DB7
tQUIET
10
DB2
11
12
t5
DB1
DB0
t6
THREE-STATE
NOTES
1. EOC IS THE END OF A CONVERSION.
Figure 27. Serial Port Timing Without Busy Indicator
Rev. B | Page 16 of 20
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