AD5680 View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

AD5680

5 V 18-Bit nanoDAC® in a SOT-23

Analog Devices 

AD5680

Data Sheet

SERIAL INTERFACE

The AD5680 has a 3-wire serial interface (SYNC, SCLK, and

DIN) that is compatible with SPI, QSPI, and MICROWIRE

interface standards as well as with most DSPs. See Figure 2 for

a timing diagram of a typical write sequence.

The write sequence begins by bringing the SYNC line low. Data

from the DIN line is clocked into the 24-bit shift register on the

falling edge of SCLK. The serial clock frequency can be as high

as 30 MHz, making the AD5680 compatible with high speed

DSPs. On the 24th falling clock edge, the last data bit is clocked

in and the programmed function is executed, that is, a change

in DAC register contents occurs. At this stage, the SYNC line

can be kept low or brought high. In either case, it must be

brought high for a minimum of 33 ns before the next write

sequence so that a falling edge of SYNC can initiate the next

write sequence. Because the SYNC buffer draws more current

when VIN = 2 V than it does when VIN = 0.8 V, SYNC should be

idled low between write sequences for even lower power

operation. As mentioned previously, it must, however, be

brought high again just before the next write sequence.

INPUT SHIFT REGISTER

The input shift register is 24 bits wide (see Figure 26). The first

two bits are don’t care bits. Bit DB21 and Bit DB20 are reserved

bits and should be set to 0. The next 18 bits are the data bits

followed by two don’t care bits. These are transferred to the

DAC register on the 24th falling edge of SCLK.

SYNC INTERRUPT

In a normal write sequence, the SYNC line is kept low for at

least 24 falling edges of SCLK, and the DAC is updated on the

24th falling edge. However, if SYNC is brought high before the

24th falling edge, this acts as an interrupt to the write sequence.

The shift register is reset and the write sequence is seen as invalid.

Neither an update of the DAC register contents nor a change in

the operating mode occurs (see Figure 27).

POWER-ON RESET

The AD5680 family contains a power-on reset circuit that

controls the output voltage during power-up. The AD5680-1

DAC output powers up to 0 V, and the AD5680-2 DAC output

powers up to midscale. The output remains there until a valid

write sequence is made to the DAC. This is useful in applications

where it is important to know the output state of the DAC while

it is in the process of powering up.

DB23 (MSB)

X

X

0

DB0 (LSB)

0 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X

X

RESERVED BITS

DATA BITS

Figure 26. Input Register Contents

SCLK

SYNC

DIN

DB23

DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 24TH FALLING EDGE

DB23

DB0

VALID WRITE SEQUENCE:

OUTPUT UPDATES ON THE 24TH FALLING EDGE

Figure 27. SYNC Interrupt Facility

Rev. C | Page 12 of 20

Share Link: