AD5626BRMZ(RevA) View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
AD5626BRMZ Datasheet PDF : 20 Pages
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AD5626
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD 1
8 VOUT
CS 2 AD5626 7 GND
SCLK 3 TOP VIEW 6 CLR
(Not to Scale)
SDIN 4
5 LDAC
Figure 3. 8-Lead MSOP Pin Configuration
VDD 1
CS 2
SCLK 3
SDIN 4
AD5626
TOP VIEW
(Not to Scale)
8 VOUT
7 GND
6 CLR
5 LDAC
Figure 4. 8-Lead LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic
Description
1
VDD
Positive Supply. Nominal value 5 V ± 5%.
2
CS
Chip Select. Active low input.
3
SCLK
Clock Input. Clock input for the internal serial input shift register.
4
SDIN
Serial Data Input. Data on this pin is clocked into the internal serial register on positive clock edges of the
SCLK pin. The most significant bit (MSB) is loaded first.
5
LDAC
Serial Register Data Write to DAC Register. Active low input that writes the serial register data into the DAC
register. Asynchronous input.
6
CLR
Clear DAC Register. Active low digital input that clears the DAC register to zero, setting the DAC to minimum
scale. Asynchronous input.
7
GND
Ground. Analog ground for the DAC. This also serves as the digital logic ground reference voltage.
8
VOUT
Voltage Output from the DAC. Fixed output voltage range of 0 V to 4.095 V with 1 mV/LSB. An internal
temperature stabilized reference maintains a fixed full-scale voltage independent of time, temperature, and
power supply variations.
Table 5. Control Logic Truth Table1
CS2, 3 CLK2 CLR LD4 Serial Shift Register Function
H
X
H
H No effect
L
L
L
H
L
↑+
↑+ L
H
X
H
X
H
X
H
X
H
H No effect
H
H No effect
H
H Shift-register-data advanced one bit
H
H Shift-register-data advanced one bit
H
↓– No effect
H
L No effect
L
X No effect
↑+ H No effect
1 ↑+ indicates a positive logic transition; ↓– indicates a negative logic transition; X = don’t care.
2 CS and CLK are interchangeable.
3 Returning CS high avoids an additional false clock of serial data input.
4 Do not clock in serial data while LD is low.
DAC Register Function
Latched
Latched
Latched
Latched
Latched
Updated with current shift register contents
Transparent
Loaded with all zeros
Latched all zeros
Rev. A | Page 6 of 20
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