PRELIMINARY TECHNICAL DATA
AD5450/AD5451/AD5452/AD5453
Table IV. Listing of suitable ADI Precision References recommended for use with AD5450/1/2/3 DACs.
Reference Output Voltage Initial Tolerance
ADR01
ADR02
ADR03
ADR425
10 V
5V
2.5 V
5V
0.1%
0.1%
0.2%
0.04%
Temperature Drift
3ppm/oC
3ppm/oC
3ppm/oC
3ppm/oC
0.1Hz to 10Hz noise Package
20µVp-p
10µVp-p
10µVp-p
3.4µVp-p
SC70, TSOT, SOIC
SC70, TSOT, SOIC
SC70, TSOT, SOIC
MSOP, SOIC
Table V. Listing of some precision ADI Op Amps suitable for use with AD5450/1/2/3 DACs.
Part # Max Supply Voltage V
OP97 ±20
OP1177 ±18
AD8551 ±6
VOS(max)µV IB(max) nA
25
0.1
60
2
5
0.05
GBP MHz
0.9
1.3
1.5
Slew Rate V/µs
0.2
0.7
0.4
tSETTLE with AD5453
Table VI. Listing of some High Speed ADI Op Amps suitable for use with AD5450/1/2/3 DACs.
Part # Max Supply Voltage V
AD8065 ±12
AD8021 ±12
AD8038 ±5
AD9631 ±5
BW @ ACL MHz
145
200
350
320
Slew Rate V/µs
180
100
425
1300
tSETTLE with AD5453 VOS(max)µ V IB(max) nA
1500
1000
3000
10000
0.01
1000
0.75
7000
at the VREF node (voltage output node in this application)
of the DAC. This is done by using low inputs capacitance
buffer amplifiers and careful board design.
Most single supply circuits include ground as part of the
analog signal range, which in turns requires an
ampliferthat can handle rail to rail signals, there is a large
range of single supply amplifiers available from Analog
Devices.
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful
consideration of the power supply and ground return
layout helps to ensure the rated performance. The printed
circuit board on which the AD5426/AD5432/AD5443 is
mounted should be designed so that the analog and digital
sections are separated, and cofined to certain areas of the
board. If the DAC is in a system where multiple devices
require an AGND-to-DGND connection, the connection
should be made at one point only. The star ground point
should be established as close as possible to the device.
These DACs should have ample supply bypassing of 10
µF in parallel with 0.1 µF on the supply located as close
to the package as possible, ideally right up against the
device. The 0.1 µF capacitor should have low Effective
Series Resistance (ESR) and Effective Series Inductance
(ESI), like the common ceramic types that provide a low
impedance path to ground at high frequencies, to handle
transient currents due to internal logic switching. Low
ESR 1 µF to 10 µF tantalum or electrolytic capacitors
should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Fast switching signals such as clocks should be shielded
with digital ground to avoid radiating noise to other parts
of the board, and should never be run near the reference
inputs.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to
each other. This reduces the effects of feedthrough
through the board. A microstrip technique is by far the
best, but not always possible with a doublesided board. In
this technique, the component side of the board is
dedicated to ground plane while signal traces are placed
on the solder side.
It is good practice to employ compact, minimum lead
length PCB layout design. Leads to the input should be as
short as possible to minimize IR drops and stray
inductance.
The PCB metal traces between VREF and RFB should also
be matched to minimize gain error. To maximize on high
frequency performance, the I-to-V amplifier should be
located as close to the device as possible.
REV. PrD
–15–