AD5172BRMZ50 View Datasheet(PDF) - Analog Devices

Part Name

Description

MFG CO.

AD5172BRMZ50

256-Position, One-Time Programmable, Dual-Channel, I2C Digital Potentiometers

Analog Devices 

AD5172/AD5173

Data Sheet

Parameter

POWER SUPPLIES

Power Supply Range

OTP Supply Voltage9, 10

Supply Current

OTP Supply Current9, 11, 12

Power Dissipation13

Power Supply Sensitivity

DYNAMIC CHARACTERISTICS14

Bandwidth, −3 dB

Total Harmonic Distortion

VW Settling Time

Resistor Noise Voltage Density

Symbol

VDD_RANGE

VDD_OTP

IDD

IDD_OTP

PDISS

PSS

BW

THDW

tS

eN_WB

Conditions

Min

2.7

TA = 25°C

5.6

VIH = 5 V or VIL = 0 V

VDD_OTP = 5.0 V, TA = 25°C

VIH = 5 V or VIL = 0 V,

VDD = 5 V

VDD = 5 V ± 10%,

code = midscale

RAB = 10 kΩ, code = 0x80

RAB = 50 kΩ, code = 0x80

RAB = 100 kΩ, code = 0x80

VA = 1 V rms, VB = 0 V,

f = 1 kHz, RAB = 10 kΩ

VA = 5 V, VB = 0 V, ±1 LSB

error band

RWB = 5 kΩ, RS = 0 Ω

Typ1 Max

5.5

5.7

5.8

3.5

6

100

33

±0.02 ±0.08

600

100

40

0.1

2

9

Unit

V

V

µA

mA

µW

%/%

kHz

kHz

kHz

%

µs

nV/√Hz

1 Typical specifications represent average readings at 25°C and VDD = 5 V.

2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from the ideal between successive tap positions. Parts are guaranteed monotonic.

3 VA = VDD, VB = 0 V, wiper (VW) = no connect.

4 Specifications apply to all VRs.

5 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits

of ±1 LSB maximum are guaranteed monotonic operating conditions.

6 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.

7 Guaranteed by design, but not subject to production test.

8 Measured at Terminal A. Terminal A is open circuited in shutdown mode.

9 The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up to VDD.

However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-up resistors.

10 Different from the operating power supply; the power supply for OTP is used one time only.

11 Different from the operating current; the supply current for OTP lasts approximately 400 ms for one time only.

12 See Figure 30 for an energy plot during an OTP program.

13 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

14 All dynamic characteristics use VDD = 5 V.

Rev. I | Page 6 of 28

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