
LRCLK
BCLK
ADC DATA
256 BCLKs
32 BCLKs
SLOT 1
LEFT
SLOT 2
SLOT 3
SLOT 4
SLOT 5
RIGHT
SLOT 6
SLOT 7
SLOT 8
AD1839
LRCLK
BCLK
DAC DATA
MSB MSB – 1 MSB – 2
Figure 7. ADC Packed Mode 256
256 BCLKs
32 BCLKs
SLOT 1
LEFT 1
SLOT 2
LEFT 2
SLOT 3
LEFT 3
SLOT 4
SLOT 5 SLOT 6 SLOT 7
RIGHT 1 RIGHT 2 RIGHT 3
SLOT 8
ABCLK
MSB MSB – 1 MSB – 2
Figure 8. DAC Packed Mode 256
DBCLK
ALRCLK
ASDATA
MSB
MSB – 1
Figure 9. ADC Packed Mode Timing
DLRCLK
DSDATA
MSB
MSB – 1
Figure 10. DAC Packed Mode Timing
REV. B
–15–