ACT-7000SC-200F17Q View Datasheet(PDF) - Aeroflex Corporation
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MFG CO.
ACT-7000SC-200F17Q Datasheet PDF : 25 Pages
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SysClock
SysAD
SysCmd
Addr Data0 Data1
Write NData NData
Data2 Data3
NData NEOD
ValidOut*
ValidIn*
RdRdy*
WrRdy*
Release*
Figure 8 – Processor Block Write
completed an independent transaction between itself
and system memory in a system where memory is
connected directly to the SysAD bus. Normally this
transaction would be a DMA read or write from the I/O
system.
Test / Breakpoint Registers
To increase both observability and controllability of
the processor thereby easing hardware and software
debugging, a pair of Test/Break-point, or Watch,
registers, Watch1 and Watch2, have been added to
the ACT 7000SC. Each Watch register can be
separately enabled to watch for a load address, a
store address, or an instruction address. All address
comparisons are done on physical addresses. An
associated register, Watch Mask, has also been
added so that either or both of the Watch registers
can compare against an address range rather than a
specific address. The range granularity is limited to a
power of two.
When enabled, a match of either Watch register
results in an exception. If the Watch is enabled for a
load or store address then the exception is the Watch
exception as defined for the R4000 with Cause
exception code twenty-three. If the Watch is enabled
for instruction addresses then a newly defined
Instruction Watch exception is taken and the Cause
code is sixteen. The Watch register which caused the
exception is indicated by Cause bits 25..24.
Table 9 summarizes a Watch operation.
Table 9 – Watch Control Register
Performance Counters
Like the Test/Break-point capability described
above, the Performance Counter feature has been
added to improve the observability and controllability
of the processor thereby easing system debug and,
especially in the case of the performance counters,
easing system tuning.
The Performance Counter feature is implemented
using two new CP0 registers, PerfCount and
PerfControl. The PerfCount register is a 32-bit
writable counter which causes an interrupt when bit
31 is set. The PerfControl register is a 32-bit register
containing a five bit field which selects one of
twenty-two event types as well as a handful of bits
which control the overall counting function. Note that
only one event type can be counted at a time and that
counting can occur for user code, kernel code, or
both. The event types and control bits are listed in
Table 10.
Register
Bit Field/Function
63 62 61 60:36 35:2 1:0
Watch1, 2 Store Load Instr 0 Addr 0
31:2
1
0
Watch
Mask
Mask
Mask Mask
Watch Watch
2
1
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