A8508
Wide Input Voltage Range, High Efficiency
8-Channel Fault Tolerant LED Driver
Pin-out Diagrams
VDD 1
NC 2
FAULT 3
OVP 4
HVGATE 5
VSENSE 6
VIN 7
21 GATE
20 SENP
19 SENN
PAD
18 PGND
17 LED1
16 LED2
15 LED3
ET Package
SENN 1
24 PGND
SENP 2
23 LED1
GATE 3
22 LED2
VDR 4
21 LED3
COMP 5
20 LED4
MODE 6
PAD
19 AGND
EN 7
18 LED5
PWM 8
17 LED6
FSET/SYNC 9
16 LED7
ISET 10
15 LED8
VDD 11
14 VIN
FAULT 12
13 OVP
LP Package
SENN 1
SENP 2
GATE 3
VDR 4
COMP 5
MODE 6
EN 7
PWM 8
FSET/SYNC 9
ISET 10
VDD 11
FAULT 12
24 PGND
23 LED1
22 LED2
21 LED3
20 LED4
19 AGND
18 LED5
17 LED6
16 LED7
15 LED8
14 VIN
13 OVP
LW Package
Terminal List Table
Name
Number
ET
LP, LW
AGND
13
19
COMP
23
5
EN
25
7
¯F¯ ¯A ¯U ¯¯L¯ ¯T¯
3
12
FSET/SYNC 27
9
GATE
21
3
HVGATE
5
n.a.
ISET
28
10
LED1
17
23
LED2
16
22
LED3
15
21
LED4
14
20
LED5
10
18
LED6
8
17
LED7
11
16
LED8
12
15
MODE
24
6
OVP
4
13
PAD
–
–
PGND
18
24
PWM
26
8
SENN
19
1
SENP
20
2
VDD
1
11
VDR
22
4
VIN
7
14
VSENSE
6
n.a.
Function
LED ground.
Output of the error amplifier and compensation node. Connect a compensation network from this pin to ground.
Enable for the A8508.
This pin is used to indicate a fault condition. Connect a pull-up resistor between this pin and the required logic level
voltage. The pin is an open drain type configuration that will be pulled low when a fault occurs.
Frequency/synchronization pin. A resistor RFSET from this pin to ground sets the switching frequency. This pin can also
be used to synchronize two or more converters in the system.
Gate pin for driving external N-channel FET.
Input disconnect switch: gate driver
Connect the RISET resistor between this pin and ground to set the 100% LED current.
Connect the cathode of each LED string to these pins.
This pin is used to determine the mode of operation. MODE high tied to VDD allows parallel operation, and MODE low is
used for single IC operation.
This pin is used to sense an Overvoltage (OVP) condition. Connect the ROVP resistor from VOUT to this pin to adjust
the overvoltage protection.
For QFN and TSSOP packages, this exposed pad provides enhanced thermal dissipation. This pad must be connected
to the ground plane(s) of the PCB with at least 8 vias, directly in the PAD solder pad.
Power ground for the internal gate driver circuit.
PWM dimming pin. Used to control the LED intensity by using pulse width modulation. The typical PWM dimming
frequency is in the range of 100 to 1000 Hz.
Negative sense line for boost switch current sensing.
Positive sense line for boost switch current sensing.
Output of internal LDO regulator. Connect a 0.1 μF decoupling capacitor between this pin and ground.
Output of the gate driver bias voltage regulator. Connect a 0.22 μF capacitor in series with a 7.5 Ω resistor between this
pin and ground.
Input power to the A8508.
Input disconnect switch: current sense
Allegro MicroSystems, Inc.
4
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com