74LVT646PW View Datasheet(PDF) - Philips Electronics

Part Name

Description

MFG CO.

74LVT646PW

3.3V Octal bus transceiver/register (3-State)

Philips Electronics 

Philips Semiconductors

3.3V Octal bus transceiver/register (3-State)

Product specification

74LVT646

FEATURES

• Combines 74LVT245 and 74LVT574 type functions in one device

• Independent registers for A and B buses

• Multiplexed real–time and stored data

• Output capability: +64mA/–32mA

• TTL input and output switching levels

• Input and output interface capability to systems at 5V supply

• Bus-hold data inputs eliminate the need for external pull-up

resistors to hold unused inputs

• Live insertion/extraction permitted

• No bus current loading when output is tied to 5V bus

• Latch-up protection exceeds 500mA per JEDEC Std 17

• Power-up 3-State

• Power-up reset

• ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

QUICK REFERENCE DATA

SYMBOL

PARAMETER

tPLH

tPHL

CIN

CI/O

ICCZ

Propagation delay

An to Bn or Bn to An

Input capacitance

CP, S, OE, DIR

I/O capacitance

Total supply current

DESCRIPTION

The LVT646 is a high-performance BiCMOS product designed for

VCC operation at 3.3V.

This device consists of bus transceiver circuits with 3-State outputs,

D-type flip-flops, and control circuitry arranged for multiplexed

transmission of data directly from the input bus or the internal

registers.

Data on the A or B bus will be clocked into the registers as the

appropriate clock pin goes High.

Output Enable (OE) and DIR pins are provided to control the

transceiver function. In the transceiver mode, data present at the

high impedance port may be stored in either the A or B register or

both.

The Select (SAB, SBA) pins determine whether data is stored or

transferred through the device in real–time. The DIR determines

which bus will receive data when the OE is active (Low).

In the isolation mode (OE = High), data from Bus A may be stored in

the B register and/or data from Bus B may be stored in the A

register.

When an output function is disabled, the input function is still

enabled and may be used to store and transmit data. Only one of

the two buses, A or B may be driven at a time. The examples on the

next page demonstrate the four fundamental bus management

functions that can be performed with the 74LVT646.

CONDITIONS

Tamb = 25°C; GND = 0V

CL = 50pF; VCC = 3.3V

VI/O = 0V or 3.0V

Outputs disabled; VI/O = 0V or 3.0V

Outputs disabled; VCC = 3.6V

TYPICAL

2.8

2.7

4

10

0.13

UNIT

ns

pF

pF

mA

ORDERING INFORMATION

PACKAGES

24-Pin Plastic SOL

24-Pin Plastic SSOP Type II

24-Pin Plastic TSSOP Type I

TEMPERATURE RANGE

–40°C to +85°C

–40°C to +85°C

–40°C to +85°C

OUTSIDE NORTH AMERICA

74LVT646 D

74LVT646 DB

74LVT646 PW

NORTH AMERICA

74LVT646 D

74LVT646 DB

74LVT646PW DH

DWG NUMBER

SOT163-1

SOT399-1

SOT360-1

PIN CONFIGURATION

CPAB 1

SAB 2

DIR 3

A0 4

A1 5

A2 6

A3 7

A4 8

A5 9

A6 10

A7 11

GND 12

24 VCC

23 CPBA

22 SBA

21 OE

20 B0

19 B1

18 B2

17 B3

16 B4

15 B5

14 B6

13 B7

SV00045

PIN DESCRIPTION

PIN NUMBER

SYMBOL

1, 23

CPAB /

CPBA

2, 22

SAB / SBA

3

4, 5, 6, 7, 8, 9, 10,

11

20, 19, 18, 17, 16,

15, 14, 13

DIR

A0 – A7

B0 – B7

21

OE

12

GND

24

VCC

FUNCTION

A to B clock input / B to A

clock input

A to B select input / B to

A select input

Direction control input

Data inputs/outputs (A

side)

Data inputs/outputs (B

side)

Output enable input

(active-low)

Ground (0V)

Positive supply voltage

1998 Feb 19

2

853-1747 18987

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