
SN54/74LS192 • SN54/74LS193
STATE DIAGRAMS
0
1
2
3
4
15
5
14
6
13
7
12
11
10
9
8
LS192
LS192 LOGIC EQUATIONS
FOR TERMINAL COUNT
TCU = Q0 ⋅ Q3 ⋅ CPU
TCD = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ CPD
LS193 LOGIC EQUATIONS
FOR TERMINAL COUNT
TCU = Q0 ⋅ Q1⋅ Q2⋅ Q3 ⋅ CPU
TCD = Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 ⋅ CPD
COUNT UP
COUNT DOWN
0
1
2
3
4
15
5
14
6
13
7
12
11
10
9
8
LS193
LOGIC DIAGRAMS
PL 11
(LOAD)
5
CPU
(UP COUNT)
P0
15
P1
1
P2
10
P3
9
12 TCU
(CARRY
OUTPUT)
SD Q
T
Q
CD
SD Q
T
Q
CD
SD Q
T
Q
CD
SD Q
T
Q
CD
CPD 4
(DOWN
COUNT)
14
MR
(CLEAR)
VCC = PIN 16
GND = PIN 8
= PIN NUMBERS
3
Q0
2
Q1
LS192
6
Q2
13 TCD
(BORROW
OUTPUT)
7
Q3
FAST AND LS TTL DATA
5-352