Philips Semiconductors
Phase-locked-loop with lock detector
Product specification
74HC/HCT7046A
Demodulator section
Voltages are referenced to GND (ground = 0 V)
Tamb (°C)
TEST CONDITIONS
SYMBOL
PARAMETER
74HCT
+25
−40 to +85
−40 to +125
UNIT VCC
(V)
min. typ. max. min. max. min. max.
OTHER
RS
resistor range
50
300
VOFF
offset voltage
±20
VCOIN to VDEMOUT
kΩ 4.5 at RS > 300 kΩ the
leakage current can
influence VDEMOUT
mV 4.5 VI = VVCOIN = 1/2
VCC; values taken
over RS range;
see Fig.13
RD
dynamic output
25
resistance at DEMOUT
Ω
4.5 VDEMOUT = 1/2 VCC
AC CHARACTERISTICS FOR 74HCT
Phase comparator section
GND = 0 V; tr = tf = 6 ns; CL = 50 pF
SYMBOL PARAMETER
tPHL/ tPLH
tPZH/ tPZL
tPHZ/ tPLZ
tTHL/ tTLH
propagation delay
SIGIN, COMPIN
to PC1OUT
3-state output enable
time SIGIN, COMPIN
to PC2OUT
3-state output disable
time SIGIN, COMPIN
to PC2OUT
output transition time
Tamb (°C)
TEST
CONDITIONS
74HCT
UNIT
+25
−40 to +85 −40 to +125
VCC
(V)
min. typ. max. min. max. min. max.
OTHER
21 40
50
60 ns 4.5 Fig.14
27 56
70
84 ns 4.5 Fig.15
35 65
81
98 ns 4.5 Fig.15
7 15
19
22 ns 4.5 Fig.14
VI(p-p)
AC coupled input sensitivity
15
(peak-to-peak value) at
SIGIN or COMPIN
mV 4.5
fi =
1 MHz
December 1990
18