74HC165(2017) View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
74HC165 Datasheet PDF : 22 Pages
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Nexperia
74HC165; 74HCT165
8-bit parallel-in/serial out shift register
Symbol Parameter Conditions
fmax
maximum
CP input; see Figure 7
frequency
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
CPD
power
per package;
dissipation
VI = GND to VCC - 1.5 V
capacitance
25 °C
Min Typ Max
-40 °C to
+85 °C
Min Max
-40 °C to Unit
+125 °C
Min Max
26 44
-
21
-
17
- MHz
-
48
-
-
-
-
- MHz
[3] -
35
-
-
-
-
- pF
[1] tpd is the same as tPHL and tPLH.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi + Σ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
Σ (CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in V.
11.1 Waveforms and test circuit
1/fmax
VI
CP or CE input
VM
GND
tW
VOH
Q7 or Q7 output
VOL
tPHL
90 %
VM
10 %
tPLH
10 %
90 %
tTHL
tTLH
mna987
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Figure 7. The clock (CP) or clock enable (CE) to output (Q7 or Q7) propagation delays, the clock pulse width, the
maximum clock frequency and the output transition times
74HC_HCT165
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 21 August 2017
© Nexperia B.V. 2017. All rights reserved.
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