74F899QC View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
MFG CO.
74F899QC Datasheet PDF : 12 Pages
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Function Table
Inputs
GAB GBA SEL LEA LEB
Operation
H
H X X X Busses A and B are 3-STATE.
H
L
L L H Generates parity from B[0:7] based on O/E (Note 1). Generated parity → APAR.
Generated parity checked against BPAR and output as ERRB.
H
L
L H H Generates parity from B[0:7] based on O/E. Generated parity → APAR. Generated
parity checked against BPAR and output as ERRB. Generated parity also fed back
through the A latch for generate/check as ERRA.
H
L
L
H
LH
H
LH
L
H
L
L
H
L
L
H
L
L
HH
L
HH
H = HIGH Voltage Level
Note 1: O/E = ODD/EVEN
X L Generates parity from B latch data based on O/E. Generated parity → APAR.
Generated parity checked against latched BPAR and output as ERRB.
X H BPAR/B[0:7] → APAR/A0:7] Feed-through mode. Generated parity checked against
BPAR and output as ERRB.
H H BPAR/B[0:7] → APAR/A[0:7]
Feed-through mode. Generated parity checked against BPAR and output as ERRB.
Generated parity also fed back through the A latch for generate/check as ERRA.
H L Generates parity for A[0:7] based on O/E. Generated parity → BPAR. Generated parity
checked against APAR and output as ERRA.
H H Generates parity from A[0:7] based on O/E. Generated parity → BPAR. Generated
parity checked against APAR and output as ERRA. Generated parity also fed back
through the B latch for generate/check as ERRB.
L X Generates parity from A latch data based on O/E. Generated parity → BPAR.
Generated parity checked against latched APAR and output as ERRA.
H L APAR/A[0:7] → BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and output as ERRA.
H H APAR/A[0:7] → BPAR/B[0:7]
Feed-through mode. Generated parity checked against APAR and output as ERRA.
Generated parity also fed back through the B latch for generate/check as ERRB.
L = LOW Voltage Level
X = Immaterial
Functional Block Diagram
3
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