N74F173N View Datasheet(PDF) - Philips Electronics

Part Name

Description

MFG CO.

N74F173N

Quad D-type flip-flop (3-State)

Philips Electronics 

Philips Semiconductors

Quad D-type flip–flop (3-State)

Product specification

74F173

FEATURES

• Edge–triggered D–type register

• Gated clock enable for hold ”do nothing” mode

• 3–state output buffers

• Gated output enable control

• Speed upgrade of N8T10 and current sink upgrade

• Controlled output edges to minimize ground bounces

• 48mA sinking capability

DESCRIPTION

The 74F173 is a high speed 4–bit parallel load register with

clock enable control, 3–state buffered outputs, and master

reset (MR). When the two clock enable (E0 and E1) inputs

are low, the data on the D inputs is loaded into the register

simultaneously with low–to–high clock (CP) transition. When

one or both enable inputs are high one setup time before the

low–to–high clock transition, the register retains the previous

data.

TYPE

74F173

TYPICAL fmax

125MHz

Data inputs and clock enable inputs are fully edge–triggered

and must be stable only one setup time before the

low–to–high clock transition.

The master reset (MR) is an active–high asynchronous

input. When the MR is high, all four flip–flops are reset

(cleared) independently of any other input condition.

The 3–state output buffers are controlled by a 2–input NOR

gate. When both output enable (OE0 and OE1) inputs are

low, the data in the register is presented at the Q output.

When one or both OE inputs are high, the outputs are forced

to a high impedance ”off” state.

The 3–state output buffers are completely independent of

the register operation; the OE transition does not affect the

clock and reset operations.

TYPICAL SUPPLY CURRENT (TOTAL)

23mA

ORDERING INFORMATION

DESCRIPTION

16–pin plastic DIP

16–pin plastic SO

ORDER CODE

COMMERCIAL RANGE

VCC = 5V ±10%, Tamb = 0°C to +70°C

N74F173N

N74F173D

INPUT AND OUTPUT LOADING AND FAN OUT TABLE

PINS

DESCRIPTION

D0 – D3

Data inputs

CP

Clock input

E0, E1

Clock enable inputs

MR

Master reset input

OE0, OE1

Output enable inputs

Q0 – Q3

Data outputs

Note to input and output loading and fan out table

1. One (1.0) FAST unit load is defined as: 20µA in the high state and 0.6mA in the low state.

74F (U.L.) HIGH/

LOW

1.0/1.0

1.0/1.0

1.0/1.0

1.0/1.0

1.0/1.0

750/80

PKG DWG #

SOT38-4

SOT109-1

LOAD VALUE

HIGH/LOW

20µA/0.6mA

20µA/0.6mA

20µA/0.6mA

20µA/0.6mA

20µA/0.6mA

15mA/48mA

August 31, 1990

2

853–1160 00286

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