74AVC16835 View Datasheet(PDF) - Philips Electronics

Part Name

Description

MFG CO.

74AVC16835

18-bit registered driver (3-State)

Philips Electronics 

Philips Semiconductors

18-bit Registered Driver (3-State)

Preliminary specification

74AVC16835

FEATURES

• Wide supply voltage range of 1.2 V to 3.6 V

• Complies with JEDEC standard no. 8-1A/5/7.

• CMOS low power consumption

• Input/output tolerant up to 3.6 V

• DCO (Dynamic Controlled Output) circuit dynamically changes

output impedance, resulting in noise reduction without speed

degradation

• Low inductance multiple VCC and GND pins for minimum noise

and ground bounce

• Power off disables 74AVC16835 outputs, permitting Live Insertion

DESCRIPTION

The 74AVC16835 is a 18-bit universal bus driver. Data flow is

controlled by output enable (OE), latch enable (LE) and clock inputs

(CP).

This product is designed to have an extremely fast propagation

delay and a minimum amount of power consumption.

To ensure the high-impedance state during power up or power

down, OE should be tied to VCC through a pullup resistor (Live

Insertion).

A Dynamic Controlled Output (DCO) circuitry is implemented to

support termination line drive during transient. See the graphs on

page 8 for typical curves.

PIN CONFIGURATION

NC 1

NC 2

Y0 3

GND 4

Y1 5

Y2 6

VCC 7

Y3 8

Y4 9

Y5 10

GND 11

Y6 12

Y7 13

Y8 14

Y9 15

Y10 16

Y11 17

GND 18

Y12 19

Y13 20

Y14 21

VCC 22

Y15 23

Y16 24

GND 25

Y17 26

OE 27

LE 28

56 GND

55 NC

54 A0

53 GND

52 A1

51 A2

50 VCC

49 A3

48 A4

47 A5

46 GND

45 A6

44 A7

43 A8

42 A9

41 A10

40 A11

39 GND

38 A12

37 A13

36 A14

35 VCC

34 A15

33 A16

32 GND

31 A17

30 CP

29 GND

SH00130

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.0 ns; CL = 30 pF.

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

tPHL/tPLH

Propagation delay

An to Yn

VCC = 1.8 V

VCC = 2.5 V

VCC = 3.3 V

2.6

2.0

1.7

Propagation delay

VCC = 1.8 V

2.8

tPHL/tPLH

LE to Yn;

VCC = 2.5 V

2.2

CP to Yn

VCC = 3.3 V

1.8

CI

Input capacitance

CPD

Power dissipation capacitance per buffer

VI = GND to VCC1

5.0

Outputs enabled

25

Output disabled

6

NOTES:

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF;

fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.

UNIT

ns

ns

pF

pF

ORDERING INFORMATION

PACKAGES

56-Pin Plastic Thin Shrink Small Outline (TSSOP) Type II

TEMPERATURE

RANGE

–40°C to +85°C

ORDER CODE

74AVC16835 DGG

DRAWING

NUMBER

SOT364-1

1999 Jul 23

2

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