74ALVC16601GX View Datasheet(PDF) - Fairchild Semiconductor
Part Name
Description
MFG CO.
74ALVC16601GX
Fairchild Semiconductor
74ALVC16601GX Datasheet PDF : 8 Pages
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Connection Diagrams
Pin Assignment for TSSOP
Pin Assignment for FBGA
(Top Thru View)
Pin Descriptions
Pin Names
Description
OEAB, OEBA
Output Enable Inputs (Active LOW)
LEAB, LEBA
Latch Enable Inputs
CLKAB, CLKBA
Clock Inputs
CLKENAB, CLKENBA Clock Enable Inputs
A1–A18
B1–B18
Side A Inputs or 3-STATE Outputs
Side B Inputs or 3-STATE Outputs
FBGA Pin Assignments
1
2
3
4
5
6
A
A2
A1 OEAB CLKENAB B1
B2
B
A4
A3 LEAB CLKAB B3
B4
C
A6
A5
VCC
VCC
B5
B6
D
A8
A7 GND GND
B7
B8
E
A10
A9 GND
GND
B9
B10
F
A12 A11 GND
GND
B11 B12
G
A14 A13 VCC
VCC
B13 B14
H
A16 A15 OEBA CLKBA B15 B16
J
A17 A18 LEBA CLKENBA B18 B17
Truth Table
(Note 4)
Inputs
Outputs
CLKENAB OEAB LEAB CLKAB An
Bn
X
H
X
X
X
Z
X
L
H
X
L
L
X
L
H
X
H
H
H
L
L
X
X B0 (Note 5)
H
L
L
X
X B0 (Note 5)
L
L
L
↑
L
L
L
L
L
↑
H
H
L
L
L
L
X B0 (Note 5)
L
L
L
H
X
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial (HIGH or LOW, inputs may not float)
Z = High Impedance
B0 (Note 6)
Note 4: A-to-B data flow is shown; B-to-A flow is similar but uses OEBA,
LEBA, CLKBA, and CLKENBA.
Note 5: Output level before the indicated steady-state input conditions
were established.
Note 6: Output level before the indicated steady-state input conditions
were established, provided that CLKAB was HIGH before LEAB went LOW.
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