Philips Semiconductors
8-bit serial-in parallel-out shift register
Product specification
74ALS164
LOGIC DIAGRAM
1
Dsa
Dsb 2
VCC = Pin 14
GND = Pin 7
CP 8
MR 9
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
DQ
CP
RD
3
Q0
4
Q1
5
Q2
6
Q3
10
Q4
11
Q5
12
Q6
13
Q7
SF00715
MODE SELECT FUNCTION TABLE
INPUTS
OUTPUTS
MR CP Dsa Dsb Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
OPERATING MODE
L
X
X
X
L
L
L
L
L
L
L
L
Reset (Clear)
H
↑
l
l
L
q0
q1
q2 q3
q4
q5 q6
H
↑
l
h
L
q0
q1
q2 q3
q4
q5 q6
H
↑
h
l
L
q0
q1
q2 q3
q4
q5 q6
Shift
H
↑
h
h
H
q0
q1
q2 q3
q4
q5 q6
NOTES:
H = High voltage level
h = High voltage level one setup time prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one setup time prior to the Low-to-High clock transition
qn = Lower case letter indicate the state of the referenced output one setup time prior to the Low-to-High clock transition.
X = Don’t care
↑ = Low-to-High clock transition
APPLICATION
The 74ALS164 can be cascaded to form synchronous shift registers of longer length.
Here, two devices are combined to form a 16-bit shift register.
CLEAR
CLOCK
DATA
ENABLE
CP
MR
Dsa
74ALS164
Dsb
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Dsa
H Dsb
CP
MR
74ALS164
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
D0 D1 D2 D3 D4 D5 D6 D7
D8 D9 D10 D11 D12 D13 D14 D15
SC00063
1991 Feb 08
3